randomtest.v

mining source code written in Verilog

module randomtest(//input
			  clk1,row,col,mine,reset,
			  //output
			  rscs,
              radc,
              ra,//address
              rd,//data
              rbw,
              rwe,//write
              roe,
			  endmine,
              //data
              sramin0,//sramin1,sramin2,sramin3,
              endminebuffer
              //light1,light2,
              //input1,input2
			  );
input clk1;
input [3:0]row,col;
input [7:0]mine;
//reg [7:0]mine;//t
input reset;

input [31:0]rd;
//inout [31:0]rd;//test
output [15:0]ra;
output [3:0]rbw;
output rscs,radc,rwe,roe;
output endmine;
//output [31:0]data;
output [3:0]sramin0;//,sramin1,sramin2;//test
//output [19:0]sramin3;//test
/////
output endminebuffer;
//output [3:0]light1;
///output [7:0]light2;
//reg [3:0]light1;
//reg [7:0]light2;
//input [7:0]input1;
//input [5:0]input2;
//reg [3:0]row,col;
//reg [7:0]mine;
//reg start;
/////
///reg data;//test
reg [31:0]data;//t
wire [3:0]sramin0=data[3:0];//t
///wire [3:0]sramin1=data[7:4];//t
//wire [3:0]sramin2=data[11:8];//t
//wire [19:0]sramin3=data[31:12];//t


reg [15:0]ra;
reg endmine;
reg [3:0]rbw;
reg rscs,radc,rwe,roe;
reg [15:0]minemap; 
wire [8:0]map=(row+1)*(col+1);
reg [7:0]counter1,counter2;
reg [7:0]mineleft;
reg [2:0]random1,random2;
reg [8:0]minenumber;
reg [3:0]counters;
reg [1:0]r_or_w;
reg [1:0]a;
reg b;
reg [5:0]c;
///
reg endminebuffer;
//assign rd=rwe?32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:{31'b0000000000000000000000000000000,data};
//assign rd=rwe?32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:{31'd0,data};

always @(posedge clk1)
begin

//if(input2[5]==0) 
//	begin
//		if(input2[0]==1) 
//			begin
 //				rscs=0; radc=0; roe=0; rwe=1;
 ///				rwe=4'b1111;
 //				ra[7:0]=input1; ra[15:8]=0;
 //				light1=rd[3:0];
 //				light2=mineleft;/
//			end
//		else begin

			if(endmine==1)
    		 endminebuffer=1;
//			else endminebuffer=0;

/*

	if(reset==0)//default  
		begin
			//
			endmine=0;
			//
			counter1=0;
			counter2=0;
			rscs=0;
            radc=0;rwe=1;roe=0;
            rbw=4'b1111;
     		ra=0;
			a=0;
			b=0;start=0;
			mineleft=0;
			counters=0; data=0; 
			if(random1<7)
				random1=random1+1;
			else
				random1=0;
///////////////////////         
//     		rbw=4'b0000;
//       		radc=0;rwe=0;roe=1;
//            ra=ra+1;
/////////////////////								
		end

	if(b==1 && reset==1)
		begin
			counter1=0;
			counter2=0;
			rscs=0;
     		radc=1;rwe=1;roe=1;
    		ra=0;
     		rbw=4'b1111;
			a=0;
			if(counters<15)
				counters=counters+1;
			else if(counters==15)
				endmine=0;			
		end
*/
	 if(reset==1 && b==0)
		begin
			if(a==2'd0)
				begin
					if(ra<256)
					begin
						rscs=0;//write
     					radc=0;rwe=0;roe=1;
						rbw=4'b0000;
						data=0;
						ra=ra+1;
					end
					if(ra==256)
					begin
						rscs=0;  //nothing
			     		radc=1;rwe=1;roe=1;
     					rbw=4'b1111;		
						if(mine<=map)
							minenumber=mine;
						else
							minenumber=map;
						if(minenumber==0) 
							begin
								b=1;
								endmine=1;
							end
						else begin
								a=2'd1;
								ra=0;
							end
					end
				    
                 end
			else if (a==2'd1)
				begin
					//if(mine<=map)
					//	minenumber=mine;
					//else
					//	minenumber=map;
					
			//		if(minenumber==0) b=1;
			//		else 
			//			begin
						rscs=0;  //nothing
			     		radc=1;rwe=1;roe=1;
     					rbw=4'b1111;		

							counter1=counter1+random1+1;
                         //   if(~(random2>counter2+7)) 
   							counter2=counter2-random2+7;
							if(counter1>(map-1))
								begin
									random1=random1+1;
									if(random1==7) random1=0;
								end
							if(counter2>(map-1))	
								begin
									random2=random2+1;
									if(random2==6) random2=0;
								end
							if(counter1>=map)	counter1=0;
							if(counter2>=map)	counter2=0;
							c=counter1-counter2;			
							if((c<=3 && c>=0) || c==7 || c==11 || c==17 || c==23 || c==31 || c==37 || c==41)
								begin
									if(counter1<map)
										begin
											ra=counter1;
											a=2'd2;
										end
									
								end
			//			end						
				 end
			else if(a==2'd2)
				begin	
					if(r_or_w==2'd0)
						begin  //read
							rscs=0;
     						radc=0;rwe=1;roe=0;
     						rbw=4'b1111;
								//ra=counter1;
							r_or_w=2'd1;
						end
					else if(r_or_w==2'd1)
						r_or_w=2'd2;
					else if(r_or_w==2'd2)
							begin
								if(rd[0]==1)
									begin
										a=1;
										r_or_w=0;
									//	rscs=0;
									//	radc=1;rwe=1;roe=1;
     								//	rbw=4'b1111;
									end
							   if(rd[0]==0)		
										r_or_w=2'd3;
							 end
					if(r_or_w==2'd3)
							begin  //write
								rscs=0;
     							radc=0;rwe=0;roe=1;
								rbw=4'b0000;
								data=1;							
								mineleft=mineleft+1;
								if(mineleft==minenumber)
									begin
										b=1;
										endmine=1;
									end		
								if(mineleft!=minenumber) 
									begin
										a=1;	
										r_or_w=0;
								//		rscs=0;
							     //		radc=1;rwe=1;roe=1;
     							//		rbw=4'b1111;	
									end
						 	end
				end
		end	
		

	else if(reset==0)//default  
		begin
			//
			c=0;
			endmine=0;
            endminebuffer=0;
//			counter1=0;
//			counter2=0;
			rscs=0;
            radc=1;rwe=1;roe=1;
            rbw=4'b1111;
     		ra=0;
			a=0;
			b=0;
			//start=0;
			mineleft=0;
			counters=0; 
			//data=0; 
			if(random1<7)
				random1=random1+1;
			else
				random1=0;
///////////////////////         
//     		rbw=4'b0000;
//       		radc=0;rwe=0;roe=1;
//            ra=ra+1;
/////////////////////								
		end

    else if(b==1 && reset==1)
		begin//1
			endmine=1;
//			counter1=0;
//			counter1=0;
//			counter2=0;
			rscs=0;
     		radc=1;rwe=1;roe=1;
     		rbw=4'b1111;
			a=0;
			data=0;
			/*
			if(counters<15)
				counters=counters+1;
			else if(counters==15)
				endmine=0;
			*/			
		end//1


//end	
//end
end
endmodule