ps2.v

mining source code written in Verilog

//host to device  
//reset condition first to do
module h2d( clk,
			data_to_send,msclk,reset,
			sending,msdata_out,msclk_out				
           );

input clk;    //25M
input [7:0]data_to_send;  //0xF4
input msclk;
input reset;

output msdata_out;  //one bit serial to mouse
output msclk_out;
output sending;

reg msclk_inverse;
reg [9:0]buffer;
reg [10:0]time_low_counter;
reg [3:0]bitcounter;
reg sendbits;
reg [3:0]msclk_low;
reg sending;

assign msclk_out=(!msclk_inverse);
assign msdata_out=sendbits?buffer[0]:1;

always @(posedge clk)
	begin
		msclk_low={msclk_low[1:0],msclk};
		if(msclk_inverse)
			begin
				time_low_counter=time_low_counter-1;
				if(time_low_counter==0)
				begin
					msclk_inverse=0;
                	sendbits=1;
				end
			end	
		else if(sendbits)
			begin
				if(msclk_low[2] && !msclk_low[1])
					begin
						buffer={1'b1,buffer[9:1]};
						bitcounter=bitcounter-1;
						if(bitcounter==0) 
							sendbits=0;
					end
			end
    	else   
			begin
				sending <= reset;        //posedge reset=1
				time_low_counter=11'd2500;  //clock low 100 us
				if(reset && !sending)
					begin
						buffer={~^data_to_send,data_to_send,1'b0}; //'0' is start
        		   		bitcounter=10;  
						msclk_inverse=1;            
					end
			end
	end
endmodule


//device to host
module d2h( clk,
            msdata,msclk,notsending,  
            dataout,received_new
           );
input clk;
input msdata;  
input msclk;
input notsending;  

output [7:0]dataout;
output received_new;

reg received_new;
reg [7:0]dataout;
reg [8:0]buffer;
reg [3:0]bitcount;
reg [2:0]msclk_low;
reg [2:0]msdata_register;
reg receiving; 
wire sending = !notsending;

always @(posedge clk or posedge sending)   //always + @ =>remember to have another blanket
	if(sending)       
		receiving=0;
	else begin           //start transmit
			msclk_low={msclk_low[1:0],msclk};
			msdata_register={msdata_register[1:0],msdata};
			if(msclk_low[2] && !msclk_low[1] )   //falling edge
				begin
					if(receiving) 
	 					begin
							if(bitcount<4'd9)		
								begin
									buffer={msdata_register[2],buffer[8:1]};   //start "0"+dataout[7:0]
									bitcount=bitcount+4'd1;
								end
							else
								begin
									receiving=0;
									if(msdata_register[2] && (^buffer[8:0])) //stop && odd parity 
										begin							
											dataout=buffer[7:0];
											received_new = !received_new;
										end							
								end
						end		
					else if(!msdata_register[2] && !receiving)  //start?
					begin
						receiving=1;
						bitcount=0;
					end
				end
		 end	
endmodule


				 									
module ps2(clk,
           msdata,msclk,row,col,
           rightbtn,leftbtn,x_position,y_position
           );
input clk;
inout msdata;           
inout msclk;         
input [3:0]row,col;

output [3:0]x_position;
output [3:0]y_position;   //mouse position
output rightbtn,leftbtn;

reg msclk_out;
reg [23:0]packet;
reg rightbtn,leftbtn;
reg [1:0]count;
reg [7:0]data;
reg [3:0]x_position,y_position;
reg [23:0]time_round;
reg received_new;
reg a,b;           //last reveived_new value
wire sending;
wire msdata_out;
wire timeout= !msclk;
wire time_out=time_round[23];
reg [2:0]counterx;

always @(posedge clk)
	begin
		if(timeout)       
			time_round=0;
		else
			time_round=time_round+1;    

		b=a^received_new;
		if(b==1)
			begin   
				count=(count<2)?(count+1):0;
				case(count)
					2'd1: packet[7:0]=data[7:0];
					2'd2: packet[15:8]=data[7:0];
					default:begin
								packet[23:16]=data[7:0];
								leftbtn=packet[0];
								rightbtn=packet[1];
								counterx=counterx+1;
									begin
										if(!packet[0] && !packet[1])
											begin
												if(counterx==7)
													begin
											//			if(packet[15:8]>packet[23:16])
											//				begin
														  		if(packet[4]==0)
																	begin if(x_position<=(row-1))
																			x_position=x_position+1;
										   						 		  else if(x_position>(row-1))
																			x_position=row;
																	end
																else
																	begin if(x_position>=1)
																			x_position=x_position-1;
										 						  		  else if(x_position<1)
																			x_position=0;
																	end
												//			end
												//		else begin
																if(packet[5]==1)
																	begin if(y_position<=(col-1))
																			y_position=y_position+1;
										   						  		  else if(y_position>(col-1))
																			y_position=col;
																	end
																else
																	begin if(y_position>=1)
																			y_position=y_position-1;
										 								  else if(y_position<1)
																	 		y_position=0;
																	end
													//	     end
													counterx=0;
												end
											end
									end
							end	
				endcase					
			a=received_new;
			end			
	end

	d2h device_to_host( clk, msdata, msclk, !sending, data, received_new);

	h2d host_to_device(clk, 8'hF4, msclk, time_out, sending, msdata_out, msclk_out);		

	TRI		op1( 0, !msdata_out, msdata );	// open collector output
	TRI		op2( 0, !msclk_out, msclk );
   
endmodule