📄 settime.rpt
字号:
- 7 - I 18 OR2 s 3 0 0 1 ~2170~4
- 8 - I 18 OR2 s 3 0 0 1 ~2170~5
- 1 - I 18 OR2 s 0 4 0 3 ~2170~6
- 5 - I 13 OR2 s 0 4 0 2 ~2305~1
- 6 - I 13 OR2 s 0 3 0 2 ~2305~2
- 8 - I 25 OR2 s 2 2 0 2 ~2305~3
- 4 - I 13 OR2 0 4 0 1 :2305
- 7 - I 13 OR2 s 0 4 0 1 ~2307~1
- 3 - I 13 OR2 0 2 0 2 :2307
- 1 - I 13 OR2 0 4 0 2 :2308
- 8 - I 13 OR2 s 0 4 0 2 ~2309~1
- 2 - I 13 OR2 0 4 0 2 :2309
- 5 - I 02 OR2 0 4 0 1 :2310
- 1 - I 23 OR2 ! 2 1 0 8 :2371
- 3 - D 24 OR2 ! 2 1 0 8 :2372
- 7 - I 06 OR2 2 1 0 6 :2373
- 5 - D 24 OR2 ! 2 1 0 8 :2374
- 5 - I 06 AND2 0 4 0 1 :2470
- 8 - I 06 AND2 s 0 3 0 1 ~2542~1
- 2 - I 06 AND2 s 0 3 0 1 ~2542~2
- 6 - I 06 OR2 0 4 0 1 :2542
- 3 - I 06 OR2 0 4 0 2 :2544
- 1 - I 06 OR2 s 0 4 0 1 ~2545~1
- 4 - I 06 OR2 0 4 0 2 :2546
- 3 - I 02 OR2 0 4 0 1 :2547
- 4 - I 14 OR2 s 0 4 0 1 ~2574~1
- 6 - I 10 OR2 s 0 4 0 1 ~2576~1
- 5 - I 23 OR2 s 0 4 0 1 ~2578~1
- 8 - I 16 OR2 ! 2 1 0 8 :2611
- 4 - I 16 OR2 ! 2 1 0 8 :2612
- 5 - I 04 OR2 2 1 0 6 :2613
- 5 - I 16 OR2 ! 2 1 0 8 :2614
- 2 - I 16 AND2 0 4 0 1 :2706
- 2 - I 23 AND2 s 0 3 0 1 ~2778~1
- 3 - I 16 AND2 s 0 3 0 1 ~2778~2
- 3 - I 04 OR2 0 4 0 1 :2778
- 2 - I 04 OR2 0 4 0 2 :2780
- 3 - I 23 OR2 s 0 4 0 1 ~2781~1
- 8 - I 02 OR2 0 4 0 2 :2782
- 1 - I 02 OR2 0 4 0 1 :2783
- 5 - I 14 OR2 s 0 4 0 1 ~2810~1
- 5 - I 10 OR2 s 0 4 0 1 ~2812~1
- 4 - I 23 OR2 s 0 4 0 1 ~2814~1
- 7 - I 14 OR2 s 0 4 0 1 ~2830~1
- 4 - I 04 OR2 s 0 4 0 1 ~2831~1
- 7 - I 04 OR2 s 0 4 0 1 ~2831~2
- 8 - I 10 OR2 s 0 4 0 1 ~2832~1
- 2 - I 14 OR2 s 0 4 0 1 ~2833~1
- 3 - I 14 OR2 s 0 4 0 1 ~2833~2
- 6 - I 23 OR2 s 0 4 0 1 ~2834~1
- 3 - I 10 OR2 s 0 4 0 1 ~2835~1
- 4 - I 10 OR2 s 0 4 0 1 ~2835~2
- 4 - I 02 OR2 s 0 4 0 1 ~2836~1
- 7 - I 02 OR2 s 0 4 0 1 ~2836~2
- 1 - I 14 DFFE + 1 3 1 0 :2838
- 1 - I 04 DFFE + 1 2 1 0 :2839
- 1 - I 10 DFFE + 1 3 1 0 :2840
- 8 - I 14 DFFE + 1 2 1 0 :2841
- 7 - I 23 DFFE + 1 3 1 0 :2842
- 2 - I 10 DFFE + 1 2 1 0 :2843
- 2 - I 02 DFFE + 1 2 1 0 :2844
- 8 - I 35 DFFE + 0 3 1 0 :2874
- 7 - I 35 DFFE + 0 3 1 0 :2875
- 3 - I 35 DFFE + 0 3 1 0 :2876
- 4 - I 35 DFFE + 0 3 1 0 :2877
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 2/208( 0%) 3/104( 2%) 0/104( 0%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 32/208( 15%) 45/104( 43%) 2/104( 1%) 4/16( 25%) 9/16( 56%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 22 t_clk
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** EQUATIONS **
d_second0 : INPUT;
d_second1 : INPUT;
d_second2 : INPUT;
d_second3 : INPUT;
d_second4 : INPUT;
d_second5 : INPUT;
d_second6 : INPUT;
d_second7 : INPUT;
t_clk : INPUT;
t_en : INPUT;
t_sw0 : INPUT;
t_sw1 : INPUT;
t_sw2 : INPUT;
t_sw3 : INPUT;
t_sw4 : INPUT;
t_sw5 : INPUT;
t_sw6 : INPUT;
t_sw7 : INPUT;
-- Node name is 'display_time0'
-- Equation name is 'display_time0', type is output
display_time0 = GND;
-- Node name is 'display_time1'
-- Equation name is 'display_time1', type is output
display_time1 = _LC2_I2;
-- Node name is 'display_time2'
-- Equation name is 'display_time2', type is output
display_time2 = _LC2_I10;
-- Node name is 'display_time3'
-- Equation name is 'display_time3', type is output
display_time3 = _LC7_I23;
-- Node name is 'display_time4'
-- Equation name is 'display_time4', type is output
display_time4 = _LC8_I14;
-- Node name is 'display_time5'
-- Equation name is 'display_time5', type is output
display_time5 = _LC1_I10;
-- Node name is 'display_time6'
-- Equation name is 'display_time6', type is output
display_time6 = _LC1_I4;
-- Node name is 'display_time7'
-- Equation name is 'display_time7', type is output
display_time7 = _LC1_I14;
-- Node name is ':68' = 'round0'
-- Equation name is 'round0', location is LC2_I35, type is buried.
round0 = DFFE(!round0, GLOBAL( t_clk), VCC, VCC, VCC);
-- Node name is ':67' = 'round1'
-- Equation name is 'round1', location is LC1_I35, type is buried.
round1 = DFFE( _EQ001, GLOBAL( t_clk), VCC, VCC, VCC);
_EQ001 = round0 & !round1
# !round0 & round1;
-- Node name is 't_diswork'
-- Equation name is 't_diswork', type is output
t_diswork = _LC2_D24;
-- Node name is 't_scan0'
-- Equation name is 't_scan0', type is output
t_scan0 = _LC4_I35;
-- Node name is 't_scan1'
-- Equation name is 't_scan1', type is output
t_scan1 = _LC3_I35;
-- Node name is 't_scan2'
-- Equation name is 't_scan2', type is output
t_scan2 = _LC7_I35;
-- Node name is 't_scan3'
-- Equation name is 't_scan3', type is output
t_scan3 = _LC8_I35;
-- Node name is 't_sec0'
-- Equation name is 't_sec0', type is output
t_sec0 = _LC6_I16;
-- Node name is 't_sec1'
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