📄 settime.rpt
字号:
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
D24 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 3/26( 11%)
I1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
I2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 19/26( 73%)
I3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 15/26( 57%)
I4 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/26( 42%)
I5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
I6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 6/26( 23%)
I7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
I9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
I10 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/26( 46%)
I13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/26( 34%)
I14 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/26( 46%)
I16 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 5/26( 19%)
I18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/26( 23%)
I22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/26( 30%)
I23 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/26( 46%)
I24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
I25 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/26( 34%)
I26 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/26( 30%)
I35 7/ 8( 87%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 0/26( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 33/327 ( 10%)
Total logic cells used: 142/4992 ( 2%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.46/4 ( 86%)
Total fan-in: 492/19968 ( 2%)
Total input pins required: 18
Total input I/O cell registers required: 0
Total output pins required: 21
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 142
Total flipflops required: 22
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 83/4992 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 1 8 8 8 1 8 8 0 8 8 0 0 8 8 0 8 0 8 0 0 0 8 8 8 8 8 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 137/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 1 8 8 8 1 8 8 0 8 8 0 0 8 8 0 8 0 8 0 0 0 8 8 13 8 8 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 142/0
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
F8 - - - 09 INPUT ^ 0 0 0 3 d_second0
E7 - - - 12 INPUT ^ 0 0 0 21 d_second1
P11 - - - -- INPUT ^ 0 0 0 22 d_second2
Y10 - - - 21 INPUT ^ 0 0 0 25 d_second3
H11 - - - -- INPUT ^ 0 0 0 25 d_second4
V11 - - - -- INPUT ^ 0 0 0 22 d_second5
E12 - - - -- INPUT ^ 0 0 0 23 d_second6
M15 - - I -- INPUT ^ 0 0 0 11 d_second7
D12 - - - -- INPUT G ^ 0 0 0 0 t_clk
R12 - - - -- INPUT ^ 0 0 0 24 t_en
P1 - - I -- INPUT ^ 0 0 0 2 t_sw0
E11 - - - 24 INPUT ^ 0 0 0 2 t_sw1
M16 - - I -- INPUT ^ 0 0 0 2 t_sw2
B9 - - - 19 INPUT ^ 0 0 0 2 t_sw3
J4 - - D -- INPUT ^ 0 0 0 2 t_sw4
N17 - - I -- INPUT ^ 0 0 0 2 t_sw5
J6 - - D -- INPUT ^ 0 0 0 2 t_sw6
Y4 - - - 02 INPUT ^ 0 0 0 2 t_sw7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
W1 - - L -- OUTPUT 0 0 0 0 display_time0
P3 - - I -- OUTPUT 0 1 0 0 display_time1
W7 - - - 10 OUTPUT 0 1 0 0 display_time2
R7 - - I -- OUTPUT 0 1 0 0 display_time3
P5 - - I -- OUTPUT 0 1 0 0 display_time4
P21 - - I -- OUTPUT 0 1 0 0 display_time5
E3 - - A -- OUTPUT 0 1 0 0 display_time6
G7 - - - 14 OUTPUT 0 1 0 0 display_time7
J5 - - D -- OUTPUT 0 1 0 0 t_diswork
U14 - - - 35 OUTPUT 0 1 0 0 t_scan0
U15 - - - 36 OUTPUT 0 1 0 0 t_scan1
R21 - - I -- OUTPUT 0 1 0 0 t_scan2
P18 - - I -- OUTPUT 0 1 0 0 t_scan3
AB8 - - - 15 OUTPUT 0 1 0 0 t_sec0
P19 - - I -- OUTPUT 0 1 0 0 t_sec1
B8 - - - 16 OUTPUT 0 1 0 0 t_sec2
P2 - - I -- OUTPUT 0 1 0 0 t_sec3
J1 - - D -- OUTPUT 0 1 0 0 t_sec4
P6 - - I -- OUTPUT 0 1 0 0 t_sec5
K7 - - D -- OUTPUT 0 1 0 0 t_sec6
G10 - - - 24 OUTPUT 0 1 0 0 t_sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime.rpt
settime
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 24 DFFE + 1 0 1 0 :47
- 8 - I 23 DFFE + 2 0 1 1 :49
- 8 - D 24 DFFE + 2 0 1 1 :50
- 8 - I 04 DFFE + 2 0 1 1 :51
- 6 - D 24 DFFE + 2 0 1 1 :52
- 1 - I 16 DFFE + 2 0 1 1 :53
- 7 - I 16 DFFE + 2 0 1 1 :54
- 6 - I 04 DFFE + 2 0 1 1 :55
- 6 - I 16 DFFE + 2 0 1 1 :56
- 1 - I 35 DFFE + 0 1 0 22 round1 (:67)
- 2 - I 35 DFFE + 0 0 0 23 round0 (:68)
- 5 - I 26 OR2 s 3 0 0 3 ~176~1
- 7 - I 03 AND2 2 2 0 2 :176
- 1 - I 01 AND2 s 2 0 0 5 ~283~1
- 8 - I 07 OR2 s 4 0 0 1 ~283~2
- 2 - I 05 AND2 s 2 0 0 4 ~390~1
- 6 - I 26 OR2 s 3 1 0 2 ~390~2
- 7 - I 07 OR2 s 2 2 0 1 ~497~1
- 4 - I 07 AND2 2 1 0 3 :497
- 3 - I 26 AND2 s 3 0 0 1 ~604~1
- 2 - I 22 OR2 s 4 0 0 1 ~604~2
- 8 - I 26 OR2 s 3 0 0 1 ~711~1
- 2 - I 26 AND2 2 2 0 2 :711
- 8 - I 09 AND2 s 3 1 0 1 ~818~1
- 1 - I 09 OR2 s 1 3 0 2 ~818~2
- 6 - I 09 AND2 s 2 0 0 1 ~925~1
- 7 - I 09 OR2 s ! 3 0 0 2 ~925~2
- 3 - I 09 AND2 2 2 0 3 :925
- 4 - I 26 AND2 2 2 0 2 :1032
- 8 - I 22 AND2 s 4 0 0 1 ~1139~1
- 1 - I 26 AND2 s 2 1 0 1 ~1139~2
- 1 - I 22 OR2 2 2 0 2 :1139
- 6 - I 03 OR2 s 0 4 0 2 ~1167~1
- 8 - I 03 OR2 s 0 3 0 2 ~1167~2
- 3 - I 07 OR2 s 1 3 0 2 ~1167~3
- 3 - I 03 OR2 0 4 0 1 :1167
- 2 - I 03 OR2 0 4 0 2 :1169
- 1 - I 03 OR2 1 3 0 2 :1170
- 5 - I 03 OR2 s 1 3 0 2 ~1171~1
- 4 - I 03 OR2 0 3 0 2 :1171
- 6 - I 02 OR2 0 4 0 1 :1172
- 6 - I 14 OR2 s 0 4 0 1 ~1199~1
- 7 - I 10 OR2 s 0 4 0 1 ~1201~1
- 5 - I 35 AND2 0 2 0 6 :1207
- 1 - I 25 AND2 s 2 0 0 6 ~1314~1
- 4 - I 25 OR2 s 2 0 0 1 ~1314~2
- 5 - I 25 OR2 s 3 1 0 1 ~1314~3
- 6 - I 25 OR2 s 3 1 0 1 ~1314~4
- 7 - I 25 OR2 s 4 0 0 1 ~1314~5
- 3 - I 25 OR2 s 2 2 0 3 ~1314~6
- 2 - I 25 AND2 s 2 0 0 5 ~1421~1
- 5 - I 22 AND2 s 4 0 0 1 ~1439~1
- 3 - I 18 OR2 s 3 0 0 1 ~1528~1
- 5 - I 09 OR2 s 2 0 0 1 ~1528~2
- 6 - I 22 OR2 s 2 2 0 1 ~1528~3
- 7 - I 22 OR2 s 4 0 0 1 ~1528~4
- 3 - I 22 OR2 s 2 2 0 4 ~1528~5
- 2 - I 24 AND2 s 4 0 0 1 ~1770~1
- 7 - I 26 AND2 s 2 0 0 1 ~1840~1
- 2 - I 18 OR2 s 4 0 0 1 ~1849~1
- 5 - I 07 OR2 s 4 0 0 1 ~1849~2
- 1 - I 07 OR2 s 2 2 0 1 ~1849~3
- 2 - I 09 OR2 s 1 3 0 3 ~1849~4
- 4 - I 09 OR2 s 3 1 0 1 ~1956~1
- 1 - I 24 OR2 s 2 2 0 1 ~1956~2
- 3 - I 24 OR2 s 2 2 0 2 ~1956~3
- 5 - I 24 OR2 0 4 0 2 :1956
- 4 - I 22 AND2 s 4 0 0 1 ~2044~1
- 6 - I 24 OR2 s 4 0 0 2 ~2063~1
- 7 - I 24 OR2 s 4 0 0 1 ~2063~2
- 8 - I 24 OR2 s 3 1 0 2 ~2063~3
- 4 - I 24 OR2 0 4 0 3 :2063
- 2 - I 07 AND2 s 3 0 0 3 ~2141~1
- 6 - I 07 AND2 s 2 0 0 1 ~2161~1
- 4 - I 18 OR2 s 3 1 0 1 ~2170~1
- 5 - I 18 AND2 s 3 0 0 1 ~2170~2
- 6 - I 18 OR2 s 3 1 0 1 ~2170~3
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