📄 traffic_light.rpt
字号:
AA9 - - - 18 OUTPUT 0 1 0 0 scan0
AB9 - - - 19 OUTPUT 0 1 0 0 scan1
U10 - - - 20 OUTPUT 0 1 0 0 scan2
V10 - - - 20 OUTPUT 0 1 0 0 scan3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\traffic_light.rpt
traffic_light
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - I 38 AND2 0 3 0 4 |adderes:added|lpm_add_sub:73|addcore:adder|:107
- 4 - I 36 AND2 0 2 0 1 |adderes:added|lpm_add_sub:73|addcore:adder|:111
- 1 - I 36 AND2 0 4 0 2 |adderes:added|lpm_add_sub:73|addcore:adder|:119
- 4 - I 28 AND2 0 2 0 3 |adderes:added|lpm_add_sub:73|addcore:adder|:123
- 5 - I 28 AND2 0 3 0 3 |adderes:added|lpm_add_sub:73|addcore:adder|:131
- 3 - I 28 AND2 0 3 0 4 |adderes:added|lpm_add_sub:73|addcore:adder|:139
- 7 - I 37 AND2 0 2 0 1 |adderes:added|lpm_add_sub:73|addcore:adder|:143
- 3 - I 37 AND2 0 4 0 2 |adderes:added|lpm_add_sub:73|addcore:adder|:151
- 4 - I 37 DFFE + 0 3 0 1 |adderes:added|:57
- 6 - I 37 DFFE + 0 2 0 2 |adderes:added|:58
- 8 - I 37 DFFE + 0 3 0 2 |adderes:added|:59
- 1 - I 37 DFFE + 0 3 0 3 |adderes:added|:60
- 2 - I 37 DFFE + 0 2 0 4 |adderes:added|:61
- 6 - I 28 DFFE + 0 3 0 2 |adderes:added|:62
- 7 - I 28 DFFE + 0 2 0 3 |adderes:added|:63
- 8 - I 28 DFFE + 0 3 0 2 |adderes:added|:64
- 1 - I 28 DFFE + 0 2 0 3 |adderes:added|:65
- 3 - I 36 DFFE + 0 2 0 2 |adderes:added|:66
- 5 - I 36 DFFE + 0 3 0 2 |adderes:added|:67
- 6 - I 36 DFFE + 0 3 0 3 |adderes:added|:68
- 8 - I 36 DFFE + 0 2 0 4 |adderes:added|:69
- 4 - I 38 DFFE + 0 3 0 2 |adderes:added|:70
- 3 - I 38 DFFE + 0 2 0 3 |adderes:added|:71
- 1 - I 38 DFFE + 0 1 0 4 |adderes:added|:72
- 1 - I 46 AND2 0 3 0 4 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:107
- 6 - I 48 AND2 0 2 0 1 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:111
- 4 - I 48 AND2 0 4 0 2 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:119
- 1 - I 48 AND2 0 2 0 3 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:123
- 4 - I 31 AND2 0 3 0 3 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:131
- 1 - I 31 AND2 0 3 0 4 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:139
- 7 - I 44 AND2 0 2 0 1 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:143
- 4 - I 44 AND2 0 4 0 2 |Counter:count|Adder:adder1|lpm_add_sub:73|addcore:adder|:151
- 5 - I 44 DFFE + 0 3 0 1 |Counter:count|Adder:adder1|:57
- 6 - I 44 DFFE + 0 2 0 2 |Counter:count|Adder:adder1|:58
- 8 - I 44 DFFE + 0 3 0 2 |Counter:count|Adder:adder1|:59
- 3 - I 44 DFFE + 0 3 0 3 |Counter:count|Adder:adder1|:60
- 1 - I 44 DFFE + 0 2 0 4 |Counter:count|Adder:adder1|:61
- 5 - I 31 DFFE + 0 3 0 2 |Counter:count|Adder:adder1|:62
- 6 - I 31 DFFE + 0 2 0 3 |Counter:count|Adder:adder1|:63
- 7 - I 31 DFFE + 0 3 0 2 |Counter:count|Adder:adder1|:64
- 2 - I 31 DFFE + 0 2 0 3 |Counter:count|Adder:adder1|:65
- 5 - I 48 DFFE + 0 2 0 2 |Counter:count|Adder:adder1|:66
- 7 - I 48 DFFE + 0 3 0 2 |Counter:count|Adder:adder1|:67
- 8 - I 48 DFFE + 0 3 0 3 |Counter:count|Adder:adder1|:68
- 3 - I 48 DFFE + 0 2 0 4 |Counter:count|Adder:adder1|:69
- 6 - I 46 DFFE + 0 3 0 2 |Counter:count|Adder:adder1|:70
- 5 - I 46 DFFE + 0 2 0 3 |Counter:count|Adder:adder1|:71
- 4 - I 46 DFFE + 0 1 0 4 |Counter:count|Adder:adder1|:72
- 8 - H 17 OR2 0 2 0 1 |Counter:count|lpm_add_sub:172|addcore:adder|pcarry1
- 5 - H 06 OR2 0 3 0 2 |Counter:count|lpm_add_sub:172|addcore:adder|pcarry2
- 6 - H 06 OR2 0 2 0 2 |Counter:count|lpm_add_sub:172|addcore:adder|pcarry3
- 7 - H 06 OR2 0 2 0 2 |Counter:count|lpm_add_sub:172|addcore:adder|pcarry4
- 4 - H 06 OR2 0 2 0 2 |Counter:count|lpm_add_sub:172|addcore:adder|pcarry5
- 5 - H 20 OR2 0 2 0 2 |Counter:count|lpm_add_sub:172|addcore:adder|pcarry6
- 3 - I 46 OR2 s 0 4 0 1 |Counter:count|~22~1
- 2 - I 44 OR2 s 0 4 0 1 |Counter:count|~22~2
- 3 - I 31 OR2 s 0 4 0 1 |Counter:count|~22~3
- 2 - I 48 OR2 s 0 4 0 1 |Counter:count|~22~4
- 2 - I 46 OR2 ! 0 4 0 10 |Counter:count|:22
- 3 - H 20 OR2 s 0 4 0 1 |Counter:count|~68~1
- 5 - H 17 OR2 s 0 4 0 1 |Counter:count|~68~2
- 1 - H 17 DFFE + 0 4 0 8 |Counter:count|first (|Counter:count|:73)
- 7 - H 20 OR2 0 3 0 3 |Counter:count|:94
- 2 - H 24 OR2 0 3 0 3 |Counter:count|:95
- 2 - H 14 OR2 0 3 0 3 |Counter:count|:96
- 1 - H 24 OR2 0 3 0 3 |Counter:count|:97
- 3 - H 17 OR2 0 3 0 3 |Counter:count|:98
- 1 - H 12 OR2 0 3 0 3 |Counter:count|:99
- 1 - H 08 OR2 0 3 0 4 |Counter:count|:100
- 3 - H 26 OR2 0 3 0 5 |Counter:count|:101
- 7 - H 17 AND2 s 0 2 0 1 |Counter:count|~126~1
- 2 - H 20 DFFE + 0 3 0 16 |Counter:count|enable (|Counter:count|:129)
- 4 - H 20 DFFE + 0 4 0 12 |Counter:count|:156
- 1 - H 20 DFFE + 0 4 0 19 |Counter:count|:157
- 2 - H 06 DFFE + 0 4 0 26 |Counter:count|:158
- 8 - H 06 DFFE + 0 4 0 21 |Counter:count|:159
- 1 - H 06 DFFE + 0 4 0 25 |Counter:count|:160
- 2 - H 17 DFFE + 0 4 0 24 |Counter:count|:161
- 3 - H 06 DFFE + 0 4 0 23 |Counter:count|:162
- 2 - H 26 DFFE + 0 3 0 4 |Counter:count|:163
- 2 - H 19 DFFE + 1 0 0 10 |SetTime:set_display|:48
- 2 - A 13 OR2 2 0 0 6 |SetTime:set_display|:73
- 6 - H 19 OR2 2 0 0 6 |SetTime:set_display|:77
- 3 - H 01 DFFE + 0 1 0 11 |SetTime:set_display|:81
- 4 - H 19 DFFE + 2 0 0 11 |SetTime:set_display|:82
- 4 - H 01 DFFE + 2 0 0 11 |SetTime:set_display|:83
- 2 - H 01 DFFE + 2 0 0 10 |SetTime:set_display|:84
- 5 - H 19 DFFE + 0 1 0 8 |SetTime:set_display|:85
- 4 - H 25 DFFE + 2 0 0 8 |SetTime:set_display|:86
- 8 - H 25 DFFE + 2 0 0 7 |SetTime:set_display|:87
- 2 - H 25 DFFE + 2 0 0 1 |SetTime:set_display|:88
- 4 - C 17 DFFE + 0 1 0 21 |SetTime:set_display|round1 (|SetTime:set_display|:91)
- 1 - C 17 DFFE + 0 0 0 22 |SetTime:set_display|round0 (|SetTime:set_display|:92)
- 6 - A 04 OR2 s ! 0 3 0 1 |SetTime:set_display|~200~1
- 4 - A 04 OR2 s 0 4 0 3 |SetTime:set_display|~200~2
- 3 - A 02 AND2 0 3 0 1 |SetTime:set_display|:200
- 2 - A 22 AND2 s 0 3 0 3 |SetTime:set_display|~307~1
- 3 - A 22 OR2 s 0 4 0 1 |SetTime:set_display|~307~2
- 7 - A 01 OR2 s 0 3 0 1 |SetTime:set_display|~414~1
- 6 - A 01 AND2 0 4 0 2 |SetTime:set_display|:414
- 7 - A 08 AND2 s 0 2 0 1 |SetTime:set_display|~521~1
- 6 - A 08 OR2 0 4 0 3 |SetTime:set_display|:521
- 5 - A 22 AND2 s 0 2 0 3 |SetTime:set_display|~628~1
- 1 - A 22 OR2 s 0 3 0 1 |SetTime:set_display|~628~2
- 1 - A 08 AND2 s 0 2 0 3 |SetTime:set_display|~628~3
- 2 - A 08 AND2 0 3 0 1 |SetTime:set_display|:628
- 2 - A 01 AND2 s 0 2 0 4 |SetTime:set_display|~735~1
- 3 - A 01 OR2 s 0 3 0 1 |SetTime:set_display|~735~2
- 8 - A 01 AND2 0 4 0 2 |SetTime:set_display|:735
- 4 - A 01 AND2 s 0 4 0 1 |SetTime:set_display|~842~1
- 5 - A 01 OR2 s 0 4 0 2 |SetTime:set_display|~842~2
- 5 - A 08 OR2 s ! 0 3 0 2 |SetTime:set_display|~949~1
- 1 - A 01 AND2 0 4 0 3 |SetTime:set_display|:949
- 5 - A 04 AND2 0 3 0 2 |SetTime:set_display|:1056
- 8 - A 04 OR2 s 0 4 0 1 |SetTime:set_display|~1163~1
- 3 - A 04 AND2 0 3 0 2 |SetTime:set_display|:1163
- 2 - A 04 OR2 s 0 3 0 2 |SetTime:set_display|~1191~1
- 2 - A 02 OR2 s 0 4 0 2 |SetTime:set_display|~1191~2
- 3 - A 08 OR2 s 0 4 0 2 |SetTime:set_display|~1191~3
- 3 - A 13 OR2 0 4 0 1 |SetTime:set_display|:1191
- 3 - A 17 OR2 0 4 0 2 |SetTime:set_display|:1193
- 1 - A 17 OR2 0 4 0 2 |SetTime:set_display|:1194
- 8 - A 20 OR2 s 0 4 0 2 |SetTime:set_display|~1195~1
- 4 - A 18 OR2 0 3 0 2 |SetTime:set_display|:1195
- 3 - A 10 OR2 0 3 0 1 |SetTime:set_display|:1196
- 6 - A 17 OR2 s 0 4 0 1 |SetTime:set_display|~1223~1
- 8 - A 18 OR2 s 0 4 0 1 |SetTime:set_display|~1225~1
- 7 - A 04 AND2 s 0 3 0 1 |SetTime:set_display|~1259~1
- 1 - A 02 AND2 s 0 2 0 3 |SetTime:set_display|~1279~1
- 3 - A 26 OR2 s 0 3 0 1 |SetTime:set_display|~1338~1
- 4 - A 26 OR2 s 0 2 0 1 |SetTime:set_display|~1338~2
- 5 - A 26 OR2 s 0 4 0 1 |SetTime:set_display|~1338~3
- 6 - A 26 OR2 s 0 4 0 1 |SetTime:set_display|~1338~4
- 2 - A 26 OR2 s 0 4 0 3 |SetTime:set_display|~1338~5
- 1 - H 26 AND2 s 0 2 0 5 |SetTime:set_display|~1445~1
- 6 - A 22 AND2 s 0 4 0 1 |SetTime:set_display|~1463~1
- 5 - A 23 OR2 s 0 4 0 1 |SetTime:set_display|~1552~1
- 2 - A 11 OR2 s 0 2 0 2 |SetTime:set_display|~1552~2
- 7 - A 22 OR2 s 0 4 0 1 |SetTime:set_display|~1552~3
- 8 - A 22 OR2 s 0 4 0 1 |SetTime:set_display|~1552~4
- 4 - A 22 OR2 s 0 4 0 4 |SetTime:set_display|~1552~5
- 5 - A 24 AND2 s 0 4 0 1 |SetTime:set_display|~1794~1
- 3 - A 23 AND2 s 0 2 0 4 |SetTime:set_display|~1864~1
- 8 - A 26 OR2 s 0 4 0 1 |SetTime:set_display|~1873~1
- 6 - A 24 OR2 s 0 4 0 1 |SetTime:set_display|~1873~2
- 7 - A 24 OR2 s 0 4 0 1 |SetTime:set_display|~1873~3
- 8 - A 24 OR2 s 0 4 0 3 |SetTime:set_display|~1873~4
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