📄 traffic_light.rpt
字号:
A6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
A8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
A9 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 6/26( 23%)
A10 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/26( 65%)
A11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
A13 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 15/26( 57%)
A14 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/26( 38%)
A15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 15/26( 57%)
A16 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/26( 46%)
A17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 15/26( 57%)
A18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 16/26( 61%)
A19 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 2/26( 7%)
A20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
A22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/26( 26%)
A23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/26( 23%)
A24 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/26( 34%)
A26 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/26( 23%)
C17 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 0/26( 0%)
F1 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 9/26( 34%)
F13 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 8/26( 30%)
F23 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 5/26( 19%)
F42 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 0/2 0/2 6/26( 23%)
F44 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/26( 15%)
F45 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 5/26( 19%)
F48 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
F49 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 1/2 0/2 5/26( 19%)
H1 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 5/26( 19%)
H4 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/26( 34%)
H6 8/ 8(100%) 6/ 8( 75%) 5/ 8( 62%) 1/2 0/2 8/26( 30%)
H7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
H8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 17/26( 65%)
H10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
H12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 18/26( 69%)
H14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 18/26( 69%)
H15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
H16 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 18/26( 69%)
H17 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 11/26( 42%)
H18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/26( 11%)
H19 4/ 8( 50%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 3/26( 11%)
H20 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 11/26( 42%)
H21 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/26( 15%)
H23 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 9/26( 34%)
H24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 18/26( 69%)
H25 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 9/26( 34%)
H26 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 0/2 15/26( 57%)
I28 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/26( 15%)
I31 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/26( 11%)
I36 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/26( 11%)
I37 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/26( 7%)
I38 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/26( 7%)
I41 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 10/26( 38%)
I44 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/26( 7%)
I46 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 5/26( 19%)
I48 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/26( 11%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 34/327 ( 10%)
Total logic cells used: 370/4992 ( 7%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.33/4 ( 83%)
Total fan-in: 1235/19968 ( 6%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 24
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 370
Total flipflops required: 95
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 160/4992 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 8 8 0 8 0 8 0 8 8 8 1 0 7 8 8 7 8 8 3 1 0 8 8 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 139/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 8 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 2 2 0 0 1 8 0 0 0 45/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 8 0 0 8 0 8 1 8 0 1 0 8 0 8 1 8 8 1 4 8 8 0 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 7 0 0 0 0 7 8 5 0 0 6 0 0 8 0 6 0 8 0 0 0 0 63/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 24 8 0 16 0 16 1 16 8 9 1 8 15 16 9 15 19 9 7 9 8 8 24 16 8 16 0 0 8 0 0 7 0 0 0 0 7 8 5 0 0 6 8 0 10 2 6 0 9 8 0 0 0 370/0
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\traffic_light.rpt
traffic_light
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
A16 - - - 43 INPUT ^ 0 0 0 2 buttom
H11 - - - -- INPUT G ^ 0 0 0 0 clock
V6 - - L -- INPUT ^ 0 0 0 18 en_sw
Y7 - - - 12 INPUT ^ 0 0 0 8 switches0
AA7 - - - 12 INPUT ^ 0 0 0 7 switches1
W7 - - - 10 INPUT ^ 0 0 0 11 switches2
U8 - - - 08 INPUT ^ 0 0 0 2 switches3
V7 - - - 07 INPUT ^ 0 0 0 8 switches4
Y4 - - - 02 INPUT ^ 0 0 0 7 switches5
AB6 - - - 11 INPUT ^ 0 0 0 11 switches6
Y6 - - - 08 INPUT ^ 0 0 0 2 switches7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\traffic_light.rpt
traffic_light
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
V9 - - - 14 OUTPUT 0 0 0 0 display_time0
V8 - - - 09 OUTPUT 0 1 0 0 display_time1
Y9 - - - 17 OUTPUT 0 1 0 0 display_time2
U9 - - - 14 OUTPUT 0 1 0 0 display_time3
AB8 - - - 15 OUTPUT 0 1 0 0 display_time4
AA8 - - - 15 OUTPUT 0 1 0 0 display_time5
W8 - - - 13 OUTPUT 0 1 0 0 display_time6
W9 - - - 18 OUTPUT 0 1 0 0 display_time7
B19 - - - 49 OUTPUT 0 1 0 0 Ecar0
C22 - - A -- OUTPUT 0 1 0 0 Ecar1
A17 - - - 43 OUTPUT 0 1 0 0 Ecar2
E17 - - - 50 OUTPUT 0 1 0 0 Eman0
P18 - - I -- OUTPUT 0 1 0 0 Eman1
F16 - - B -- OUTPUT 0 1 0 0 Eman2
A19 - - - 45 OUTPUT 0 1 0 0 Ncar0
C18 - - - 48 OUTPUT 0 1 0 0 Ncar1
B18 - - - 46 OUTPUT 0 1 0 0 Ncar2
E16 - - - 41 OUTPUT 0 1 0 0 Nman0
M16 - - I -- OUTPUT 0 1 0 0 Nman1
C16 - - - 42 OUTPUT 0 1 0 0 Nman2
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