traffic_light.v
来自「Traffic light written with Verilog」· Verilog 代码 · 共 894 行 · 第 1/2 页
V
894 行
next_state = S6;
next_check1=0;
reset=1;
end
end
else
begin
reset=1;
next_check2=0;
end
end
end
S6:
begin
check1=next_check1;
check2=next_check2;
if( check1 == 0 )
begin
count_sec = `StoR_delay;
next_check1=1;
end
else if( check2 == 0 )
begin
count_sec = next_count_sec;
next_check2=1;
end
else
begin
if( no_work == 0 )
begin
if ( dis_work == 0 )
begin
if ( count_out==0 )
begin
next_state = S7;
next_check1=0;
reset=1;
end
else
next_state = S6;
end
else
reset=1;
if ( change==1 )
begin
next_state = S7;
next_check1=0;
reset=1;
end
end
else
begin
reset=1;
next_check2=0;
end
end
end
S7:
begin
check1=next_check1;
check2=next_check2;
if( check1 == 0 )
begin
count_sec = `GtoY_delay;
next_check1=1;
end
else if( check2 == 0 )
begin
count_sec = next_count_sec;
next_check2=1;
end
else
begin
if( no_work == 0 )
begin
if ( dis_work == 0 )
begin
if ( count_out==0 )
begin
next_state = S8;
next_check1=0;
reset=1;
end
else
next_state = S7;
end
else
reset=1;
if ( change==1 )
begin
next_state = S8;
next_check1=0;
reset=1;
end
end
else
begin
reset=1;
next_check2=0;
end
end
end
S8:
begin
check1=next_check1;
check2=next_check2;
if( check1 == 0 )
begin
count_sec = `YtoR_delay;
next_check1=1;
end
else if( check2 == 0 )
begin
count_sec = next_count_sec;
next_check2=1;
end
else
begin
if( no_work == 0 )
begin
if ( dis_work == 0 )
begin
if ( count_out==0 )
begin
next_state = S9;
next_check1=0;
reset=1;
end
else
next_state = S8;
end
else
reset=1;
if ( change==1 )
begin
next_state = S9;
next_check1=0;
reset=1;
end
end
else
begin
reset=1;
next_check2=0;
end
end
end
S9:
begin
check1=next_check1;
check2=next_check2;
if( check1 == 0 )
begin
count_sec = `RtoG_delay;
next_check1=1;
end
else if( check2 == 0 )
begin
count_sec = next_count_sec;
next_check2=1;
end
else
begin
if( no_work == 0 )
begin
if ( dis_work == 0 )
begin
if ( count_out==0 )
begin
next_state = S0;
next_check1=0;
reset=1;
end
else
next_state = S9;
end
else
reset=1;
if ( change==1 )
begin
next_state = S0;
next_check1=0;
reset=1;
end
end
else
begin
reset=1;
next_check2=0;
end
end
end
default: next_state = S0;
endcase
end
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!Maybe unwork!!!!!!!!!!!!!!!!!!!!!!!!!!
always @(negedge no_work)
begin
case( t_sec[7:4] )
Zero:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd0;
One: set_sec=8'd1;
Two: set_sec=8'd2;
Three: set_sec=8'd3;
Four: set_sec=8'd4;
Five: set_sec=8'd5;
Six: set_sec=8'd6;
Seven: set_sec=8'd7;
Eight: set_sec=8'd8;
Nine: set_sec=8'd9;
default: set_sec=8'd99;
endcase
end
One:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd10;
One: set_sec=8'd11;
Two: set_sec=8'd12;
Three: set_sec=8'd13;
Four: set_sec=8'd14;
Five: set_sec=8'd15;
Six: set_sec=8'd16;
Seven: set_sec=8'd17;
Eight: set_sec=8'd18;
Nine: set_sec=8'd19;
default: set_sec=8'd0;
endcase
end
Two:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd20;
One: set_sec=8'd21;
Two: set_sec=8'd22;
Three: set_sec=8'd23;
Four: set_sec=8'd24;
Five: set_sec=8'd25;
Six: set_sec=8'd26;
Seven: set_sec=8'd27;
Eight: set_sec=8'd28;
Nine: set_sec=8'd29;
default: set_sec=8'd99;
endcase
end
Three:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd30;
One: set_sec=8'd31;
Two: set_sec=8'd32;
Three: set_sec=8'd33;
Four: set_sec=8'd34;
Five: set_sec=8'd35;
Six: set_sec=8'd36;
Seven: set_sec=8'd37;
Eight: set_sec=8'd38;
Nine: set_sec=8'd39;
default: set_sec=8'd99;
endcase
end
Four:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd40;
One: set_sec=8'd41;
Two: set_sec=8'd42;
Three: set_sec=8'd43;
Four: set_sec=8'd44;
Five: set_sec=8'd45;
Six: set_sec=8'd46;
Seven: set_sec=8'd47;
Eight: set_sec=8'd48;
Nine: set_sec=8'd49;
default: set_sec=8'd99;
endcase
end
Five:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd50;
One: set_sec=8'd51;
Two: set_sec=8'd52;
Three: set_sec=8'd53;
Four: set_sec=8'd54;
Five: set_sec=8'd55;
Six: set_sec=8'd56;
Seven: set_sec=8'd57;
Eight: set_sec=8'd58;
Nine: set_sec=8'd59;
default: set_sec=8'd99;
endcase
end
Six:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd60;
One: set_sec=8'd61;
Two: set_sec=8'd62;
Three: set_sec=8'd63;
Four: set_sec=8'd64;
Five: set_sec=8'd65;
Six: set_sec=8'd66;
Seven: set_sec=8'd67;
Eight: set_sec=8'd68;
Nine: set_sec=8'd69;
default: set_sec=8'd99;
endcase
end
Seven:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd70;
One: set_sec=8'd71;
Two: set_sec=8'd72;
Three: set_sec=8'd73;
Four: set_sec=8'd74;
Five: set_sec=8'd75;
Six: set_sec=8'd76;
Seven: set_sec=8'd77;
Eight: set_sec=8'd78;
Nine: set_sec=8'd79;
default: set_sec=8'd99;
endcase
end
Eight:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd80;
One: set_sec=8'd81;
Two: set_sec=8'd82;
Three: set_sec=8'd83;
Four: set_sec=8'd84;
Five: set_sec=8'd85;
Six: set_sec=8'd86;
Seven: set_sec=8'd87;
Eight: set_sec=8'd88;
Nine: set_sec=8'd89;
default: set_sec=8'd99;
endcase
end
Nine:
begin
case( t_sec[3:0] )
Zero: set_sec=8'd90;
One: set_sec=8'd91;
Two: set_sec=8'd92;
Three: set_sec=8'd93;
Four: set_sec=8'd94;
Five: set_sec=8'd95;
Six: set_sec=8'd96;
Seven: set_sec=8'd97;
Eight: set_sec=8'd98;
Nine: set_sec=8'd99;
default: set_sec=8'd99;
endcase
end
default: set_sec=8'd99;
endcase
next_count_sec = set_sec;
end
endmodule
module adderes( mclk, en1, count1 );
input mclk, en1;
output [15:0] count1;
reg [15:0] count1;
always @(posedge mclk)
if( en1==0 )
count1=0;
else
count1 = count1+1;
endmodule
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