📄 display.rpt
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Project Informationc:\documents and settings\no7\my documents\traffic light\display.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 03/16/2004 01:04:00
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
display EPM7096LC68-7 19 12 0 57 42 59 %
User Pins: 19 12 0
Project Informationc:\documents and settings\no7\my documents\traffic light\display.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':2723' stuck at GND
Warning: Primitive 'display_time0' is stuck at GND
Project Informationc:\documents and settings\no7\my documents\traffic light\display.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'd_clk' chosen for auto global Clock
Project Informationc:\documents and settings\no7\my documents\traffic light\display.rpt
** FILE HIERARCHY **
|lpm_add_sub:2756|
|lpm_add_sub:2756|addcore:adder|
|lpm_add_sub:2756|addcore:adder|addcore:adder0|
|lpm_add_sub:2756|altshift:result_ext_latency_ffs|
|lpm_add_sub:2756|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2756|altshift:oflow_ext_latency_ffs|
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\display.rpt
display
***** Logic for device 'display' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
d
d d d _ d
_ _ _ n _ R R R R
s s s o s E E E E
e e e _ e V S S S S
c c c c c C d E E V E E
o o o o o C _ R R C R R
n n n G u n I G G G c G V V C V V
d d d N n d N N N N l N E E I E E
1 6 7 D t 5 T D D D k D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
d_second2 | 10 60 | RESERVED
VCCIO | 11 59 | display_time3
d_second3 | 12 58 | GND
d_second4 | 13 57 | RESERVED
d_setsec0 | 14 56 | RESERVED
d_setsec1 | 15 55 | d_scan0
GND | 16 54 | d_scan1
d_second0 | 17 53 | VCCIO
d_setsec6 | 18 EPM7096LC68-7 52 | d_scan2
no_display | 19 51 | display_time1
d_setsec7 | 20 50 | d_scan3
VCCIO | 21 49 | display_time2
d_setsec5 | 22 48 | GND
display_time4 | 23 47 | display_time0
RESERVED | 24 46 | RESERVED
RESERVED | 25 45 | RESERVED
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
R R d d V d d G V R d G d R R R V
E E i _ C _ _ N C E i N i E E E C
S S s s C s s D C S s D s S S S C
E E p e I e e I E p p E E E I
R R l t O t t N R l l R R R O
V V a s s s T V a a V V V
E E y e e e E y y E E E
D D _ c c c D _ _ D D D
t 2 4 3 t t
i i i
m m m
e e e
7 5 6
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\display.rpt
display
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 7/16( 43%) 8/ 8(100%) 15/16( 93%) 29/36( 80%)
C: LC33 - LC48 10/16( 62%) 4/ 8( 50%) 16/16(100%) 24/36( 66%)
D: LC49 - LC64 10/16( 62%) 2/ 8( 25%) 16/16(100%) 32/36( 88%)
E: LC65 - LC80 14/16( 87%) 7/ 8( 87%) 15/16( 93%) 33/36( 91%)
F: LC81 - LC96 16/16(100%) 1/ 8( 12%) 16/16(100%) 25/36( 69%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 30/48 ( 62%)
Total logic cells used: 57/96 ( 59%)
Total shareable expanders used: 42/96 ( 43%)
Total Turbo logic cells used: 57/96 ( 59%)
Total shareable expanders not available (n/a): 36/96 ( 37%)
Average fan-in: 12.45
Total fan-in: 710
Total input pins required: 19
Total output pins required: 12
Total bidirectional pins required: 0
Total logic cells required: 57
Total flipflops required: 13
Total product terms required: 262
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 21
Synthesized logic cells: 43/ 96 ( 44%)
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\display.rpt
display
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 - - INPUT G 0 0 0 0 0 0 0 d_clk
5 (14) (A) INPUT 0 0 0 0 0 7 15 d_no_count
17 (27) (B) INPUT 0 0 0 0 0 3 28 d_second0
9 (8) (A) INPUT 0 0 0 0 0 5 35 d_second1
10 (6) (A) INPUT 0 0 0 0 0 6 37 d_second2
12 (4) (A) INPUT 0 0 0 0 0 6 41 d_second3
13 (1) (A) INPUT 0 0 0 0 0 6 42 d_second4
4 (16) (A) INPUT 0 0 0 0 0 7 40 d_second5
8 (9) (A) INPUT 0 0 0 0 0 7 41 d_second6
7 (12) (A) INPUT 0 0 0 0 0 7 42 d_second7
14 (32) (B) INPUT 0 0 0 0 0 5 7 d_setsec0
15 (29) (B) INPUT 0 0 0 0 0 6 8 d_setsec1
30 (37) (C) INPUT 0 0 0 0 0 3 10 d_setsec2
33 (33) (C) INPUT 0 0 0 0 0 5 12 d_setsec3
32 (35) (C) INPUT 0 0 0 0 0 6 8 d_setsec4
22 (19) (B) INPUT 0 0 0 0 0 7 7 d_setsec5
18 (25) (B) INPUT 0 0 0 0 0 6 10 d_setsec6
20 (21) (B) INPUT 0 0 0 0 0 6 12 d_setsec7
19 (24) (B) INPUT 0 0 0 0 0 7 42 no_display
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\display.rpt
display
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
47 67 E OUTPUT t 0 0 0 0 0 0 0 display_time0
51 73 E FF + t 7 7 0 16 11 0 0 display_time1
49 69 E FF + t 5 5 0 15 9 0 0 display_time2
59 86 F FF + t 6 4 0 17 7 0 0 display_time3
23 17 B FF + t 9 9 0 17 12 0 0 display_time4
37 51 D FF + t 4 4 0 9 7 0 0 display_time5
39 53 D FF + t 7 7 0 17 9 0 0 display_time6
29 40 C FF + t 7 6 0 14 10 0 0 display_time7
55 80 E FF + t 0 0 0 0 2 0 0 d_scan0
54 77 E FF + t 0 0 0 0 2 0 0 d_scan1
52 75 E FF + t 0 0 0 0 2 0 0 d_scan2
50 72 E FF + t 0 0 0 0 2 0 0 d_scan3
Code:
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