settime2.rpt

Traffic light written with Verilog

18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
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27:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
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30:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
32:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
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34:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      4/24( 16%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
36:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
37:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
38:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
39:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
40:      0/24(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
41:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
42:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
43:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
44:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
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46:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
47:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
48:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
49:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
50:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
51:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
52:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       17         t_clk


Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2

** EQUATIONS **

d_second0 : INPUT;
d_second1 : INPUT;
d_second2 : INPUT;
d_second3 : INPUT;
d_second4 : INPUT;
d_second5 : INPUT;
d_second6 : INPUT;
d_second7 : INPUT;
t_clk    : INPUT;
t_sw0    : INPUT;
t_sw1    : INPUT;
t_sw2    : INPUT;
t_sw3    : INPUT;

-- Node name is 'display_time0' 
-- Equation name is 'display_time0', type is output 
display_time0 =  GND;

-- Node name is 'display_time1' 
-- Equation name is 'display_time1', type is output 
display_time1 =  _LC6_D47;

-- Node name is 'display_time2' 
-- Equation name is 'display_time2', type is output 
display_time2 =  _LC4_E48;

-- Node name is 'display_time3' 
-- Equation name is 'display_time3', type is output 
display_time3 =  _LC3_E29;

-- Node name is 'display_time4' 
-- Equation name is 'display_time4', type is output 
display_time4 =  _LC1_E34;

-- Node name is 'display_time5' 
-- Equation name is 'display_time5', type is output 
display_time5 =  _LC1_E48;

-- Node name is 'display_time6' 
-- Equation name is 'display_time6', type is output 
display_time6 =  _LC8_E44;

-- Node name is 'display_time7' 
-- Equation name is 'display_time7', type is output 
display_time7 =  _LC8_E34;

-- Node name is 't_diswork' 
-- Equation name is 't_diswork', type is output 
t_diswork =  _LC7_D31;

-- Node name is ':42' = 't_round0' 
-- Equation name is 't_round0', location is LC6_J43, type is buried.
t_round0 = DFFE(!t_round0, GLOBAL( t_clk),  VCC,  VCC,  VCC);

-- Node name is ':41' = 't_round1' 
-- Equation name is 't_round1', location is LC1_J37, type is buried.
t_round1 = DFFE( _EQ001, GLOBAL( t_clk),  VCC,  VCC,  VCC);
  _EQ001 =  t_round0 & !t_round1
         # !t_round0 &  t_round1;

-- Node name is ':40' = 't_round2' 
-- Equation name is 't_round2', location is LC1_J43, type is buried.
t_round2 = DFFE( _EQ002, GLOBAL( t_clk),  VCC,  VCC,  VCC);
  _EQ002 = !t_round0 &  t_round2
         # !t_round1 &  t_round2
         #  t_round0 &  t_round1 & !t_round2;

-- Node name is ':39' = 't_round3' 
-- Equation name is 't_round3', location is LC3_J43, type is buried.
t_round3 = DFFE( _EQ003, GLOBAL( t_clk),  VCC,  VCC,  VCC);
  _EQ003 = !t_round0 &  t_round3
         # !t_round1 &  t_round3
         # !t_round2 &  t_round3
         #  t_round0 &  t_round1 &  t_round2 & !t_round3;

-- Node name is 't_scan0' 
-- Equation name is 't_scan0', type is output 
t_scan0  =  _LC2_J42;

-- Node name is 't_scan1' 
-- Equation name is 't_scan1', type is output 
t_scan1  =  _LC1_J42;

-- Node name is 't_scan2' 
-- Equation name is 't_scan2', type is output 
t_scan2  =  _LC2_J37;

-- Node name is 't_scan3' 
-- Equation name is 't_scan3', type is output 
t_scan3  =  _LC4_J37;

-- Node name is 't_sec0' 
-- Equation name is 't_sec0', type is output 
t_sec0   =  _LC6_D35;

-- Node name is 't_sec1' 
-- Equation name is 't_sec1', type is output 
t_sec1   =  _LC4_D35;

-- Node name is 't_sec2' 
-- Equation name is 't_sec2', type is output 
t_sec2   =  _LC2_D32;

-- Node name is 't_sec3' 
-- Equation name is 't_sec3', type is output 
t_sec3   =  _LC2_D47;

-- Node name is 't_sec4' 
-- Equation name is 't_sec4', type is output 
t_sec4   =  _LC2_D35;

-- Node name is 't_sec5' 
-- Equation name is 't_sec5', type is output 
t_sec5   =  _LC1_D35;

-- Node name is 't_sec6' 
-- Equation name is 't_sec6', type is output 
t_sec6   =  _LC6_D32;

-- Node name is 't_sec7' 
-- Equation name is 't_sec7', type is output 
t_sec7   =  _LC3_D47;

-- Node name is ':169' 
-- Equation name is '_LC8_J43', type is buried 
_LC8_J43 = LCELL( _EQ004);
  _EQ004 = !t_round0 &  t_round1 &  t_round2 &  t_round3;

-- Node name is ':178' 
-- Equation name is '_LC7_J43', type is buried 
_LC7_J43 = LCELL( _EQ005);
  _EQ005 =  t_round0 &  t_round1 &  t_round2 &  t_round3;

-- Node name is '~201~1' 
-- Equation name is '~201~1', location is LC6_J42, type is buried.
-- synthesized logic cell 
_LC6_J42 = LCELL( _EQ006);
  _EQ006 = !t_round1
         # !t_round3;

-- Node name is '~201~2' 
-- Equation name is '~201~2', location is LC3_J42, type is buried.
-- synthesized logic cell 
_LC3_J42 = LCELL( _EQ007);
  _EQ007 = !_LC4_J42 & !_LC4_J43 & !_LC5_J42 &  _LC6_J42;

-- Node name is ':201' 
-- Equation name is '_LC3_J37', type is buried 
!_LC3_J37 = _LC3_J37~NOT;
_LC3_J37~NOT = LCELL( _EQ008);
  _EQ008 =  _LC3_J42 & !_LC6_J37;

-- Node name is '~207~1' 
-- Equation name is '~207~1', location is LC2_J43, type is buried.
-- synthesized logic cell 
!_LC2_J43 = _LC2_J43~NOT;
_LC2_J43~NOT = LCELL( _EQ009);
  _EQ009 =  t_round3
         #  t_round1 &  t_round2
         # !t_round1 & !t_round2;

-- Node name is '~207~2' 
-- Equation name is '~207~2', location is LC5_J43, type is buried.
-- synthesized logic cell 
_LC5_J43 = LCELL( _EQ010);
  _EQ010 =  _LC4_J43
         #  _LC2_J43
         #  _LC7_J43
         #  _LC8_J43;

-- Node name is '~210~1' 
-- Equation name is '~210~1', location is LC5_J37, type is buried.
-- synthesized logic cell 
!_LC5_J37 = _LC5_J37~NOT;
_LC5_J37~NOT = LCELL( _EQ011);
  _EQ011 =  t_round3
         # !t_round2
         # !t_round1;

-- Node name is '~210~2' 
-- Equation name is '~210~2', location is LC6_J37, type is buried.
-- synthesized logic cell 
!_LC6_J37 = _LC6_J37~NOT;
_LC6_J37~NOT = LCELL( _EQ012);
  _EQ012 =  t_round1
         # !t_round3
         # !t_round2;

-- Node name is '~210~3' 
-- Equation name is '~210~3', location is LC7_J42, type is buried.