📄 settime2.rpt
字号:
- 7 - D 30 OR2 s 0 4 0 1 ~362~1
- 3 - D 35 OR2 s 0 4 0 1 ~362~2
- 2 - D 43 OR2 s 0 4 0 2 ~362~3
- 6 - D 51 AND2 0 4 0 17 :362
- 1 - D 47 OR2 1 2 0 1 :414
- 4 - D 47 OR2 1 2 0 2 :415
- 3 - D 31 OR2 s 0 2 0 1 ~439~1
- 3 - D 32 OR2 s 0 4 0 1 ~444~1
- 5 - D 47 OR2 0 4 0 9 :444
- 5 - D 37 OR2 1 2 0 1 :495
- 2 - D 37 OR2 1 2 0 5 :496
- 6 - D 30 OR2 1 2 0 1 :556
- 2 - D 30 OR2 1 2 0 6 :557
- 7 - D 32 OR2 1 2 0 1 :617
- 5 - D 32 OR2 1 2 0 6 :618
- 1 - D 49 OR2 s 0 2 0 3 ~648~1
- 3 - D 37 OR2 1 2 0 1 :745
- 7 - D 37 OR2 1 2 0 6 :746
- 5 - D 30 OR2 1 2 0 1 :806
- 4 - D 30 OR2 1 2 0 4 :807
- 8 - D 32 OR2 1 2 0 1 :867
- 4 - D 32 OR2 1 2 0 5 :868
- 1 - D 51 AND2 0 4 0 4 :1048
- 1 - D 37 OR2 1 2 0 1 :1100
- 4 - D 37 OR2 1 2 0 2 :1101
- 4 - D 29 AND2 ! 0 4 0 1 :1141
- 8 - D 37 OR2 s 0 4 0 4 ~1147~1
- 4 - D 45 OR2 s 0 4 0 1 ~1147~2
- 8 - D 43 OR2 s 0 4 0 1 ~1147~3
- 6 - D 37 OR2 s 0 4 0 1 ~1147~4
- 5 - D 43 OR2 0 3 0 2 :1147
- 3 - D 30 OR2 s 0 3 0 1 ~1148~1
- 1 - D 32 OR2 s 0 3 0 1 ~1148~2
- 3 - D 45 OR2 s 0 4 0 1 ~1148~3
- 5 - D 45 OR2 s 0 4 0 1 ~1148~4
- 6 - D 45 OR2 s 0 3 0 1 ~1148~5
- 7 - D 45 OR2 s 0 4 0 1 ~1148~6
- 2 - D 45 OR2 0 3 0 4 :1148
- 3 - D 43 OR2 s 0 4 0 1 ~1149~1
- 4 - D 43 OR2 s 0 4 0 1 ~1149~2
- 6 - D 43 OR2 s 0 4 0 1 ~1149~3
- 1 - D 43 OR2 0 4 0 4 :1149
- 8 - D 30 OR2 s 0 4 0 1 ~1150~1
- 1 - D 30 OR2 s 0 4 0 1 ~1150~2
- 5 - D 35 OR2 s 0 4 0 1 ~1150~3
- 7 - D 35 OR2 s 0 3 0 1 ~1150~4
- 8 - D 35 OR2 0 3 0 2 :1150
- 3 - D 47 DFFE + 0 3 1 9 :1208
- 6 - D 32 DFFE + 0 3 1 9 :1209
- 1 - D 35 DFFE + 0 3 1 7 :1210
- 2 - D 35 DFFE + 0 3 1 9 :1211
- 2 - D 47 DFFE + 0 3 1 8 :1212
- 2 - D 32 DFFE + 0 3 1 8 :1213
- 4 - D 35 DFFE + 0 3 1 6 :1214
- 6 - D 35 DFFE + 0 3 1 8 :1215
- 4 - D 51 AND2 0 4 0 7 :1256
- 2 - E 35 OR2 s 3 0 0 3 ~1362~1
- 4 - E 27 AND2 2 2 0 3 :1362
- 2 - E 37 AND2 s 2 0 0 5 ~1469~1
- 8 - E 27 OR2 s 4 0 0 1 ~1469~2
- 4 - E 33 AND2 s 2 0 0 5 ~1576~1
- 5 - E 27 OR2 s 3 0 0 2 ~1576~2
- 7 - E 27 AND2 0 3 0 1 :1576
- 7 - E 32 OR2 s 2 2 0 1 ~1683~1
- 3 - E 32 AND2 2 1 0 3 :1683
- 7 - E 51 AND2 s 3 0 0 1 ~1790~1
- 2 - E 32 OR2 s 4 0 0 1 ~1790~2
- 1 - E 27 OR2 s 3 0 0 1 ~1897~1
- 8 - E 51 AND2 2 2 0 2 :1897
- 7 - E 33 AND2 s 3 1 0 1 ~2004~1
- 6 - E 33 OR2 s 1 3 0 2 ~2004~2
- 2 - E 33 AND2 s 2 0 0 3 ~2111~1
- 5 - E 33 OR2 s ! 3 0 0 2 ~2111~2
- 8 - E 33 AND2 2 2 0 4 :2111
- 1 - E 37 AND2 2 2 0 2 :2218
- 3 - E 33 AND2 s 4 0 0 1 ~2325~1
- 5 - E 51 AND2 s 2 1 0 1 ~2325~2
- 6 - E 51 OR2 2 2 0 2 :2325
- 2 - E 51 OR2 s 0 4 0 2 ~2353~1
- 2 - E 27 OR2 s 0 4 0 2 ~2353~2
- 3 - E 27 OR2 s 1 3 0 2 ~2353~3
- 1 - E 44 OR2 0 4 0 1 :2353
- 6 - E 48 OR2 0 4 0 1 :2354
- 4 - E 51 OR2 0 4 0 2 :2355
- 3 - E 51 OR2 1 3 0 2 :2356
- 1 - E 51 OR2 s 1 3 0 3 ~2357~1
- 1 - E 29 OR2 s 0 3 0 1 ~2385~1
- 2 - E 48 OR2 s 0 4 0 1 ~2390~1
- 6 - E 27 OR2 s 0 4 0 1 ~2391~1
- 8 - D 51 AND2 0 4 0 7 :2393
- 1 - E 50 AND2 s 2 0 0 5 ~2499~1
- 3 - E 28 OR2 s 2 0 0 1 ~2499~2
- 4 - E 28 OR2 s 3 1 0 1 ~2499~3
- 5 - E 28 OR2 s 3 1 0 1 ~2499~4
- 6 - E 28 OR2 s 4 0 0 1 ~2499~5
- 7 - E 28 OR2 s 2 2 0 2 ~2499~6
- 1 - E 28 AND2 0 2 0 3 :2499
- 2 - E 50 AND2 s 2 0 0 5 ~2606~1
- 7 - E 49 AND2 s 4 0 0 1 ~2624~1
- 3 - E 35 OR2 s 3 0 0 1 ~2713~1
- 4 - E 49 OR2 s 2 0 0 3 ~2713~2
- 5 - E 49 OR2 s 4 0 0 2 ~2713~3
- 8 - E 49 OR2 s 2 2 0 2 ~2713~4
- 2 - E 49 OR2 0 4 0 2 :2713
- 3 - E 49 OR2 0 4 0 3 :2820
- 4 - E 42 AND2 s 4 0 0 1 ~2955~1
- 3 - E 37 AND2 s 2 0 0 1 ~3025~1
- 4 - E 32 OR2 s 4 0 0 1 ~3034~1
- 8 - E 32 OR2 s 4 0 0 1 ~3034~2
- 5 - E 32 OR2 s 2 2 0 1 ~3034~3
- 1 - E 49 OR2 s 1 3 0 3 ~3034~4
- 1 - E 33 OR2 s 3 1 0 1 ~3141~1
- 3 - E 42 OR2 s 0 3 0 1 ~3141~2
- 5 - E 42 OR2 s 2 2 0 2 ~3141~3
- 1 - E 42 OR2 0 4 0 2 :3141
- 6 - E 49 AND2 s 4 0 0 1 ~3229~1
- 6 - E 42 OR2 s 4 0 0 2 ~3248~1
- 7 - E 42 OR2 s 4 0 0 1 ~3248~2
- 8 - E 42 OR2 s 1 2 0 2 ~3248~3
- 2 - E 42 OR2 0 4 0 4 :3248
- 1 - E 32 AND2 s 3 0 0 3 ~3326~1
- 6 - E 32 AND2 s 2 0 0 1 ~3346~1
- 4 - E 35 OR2 s 3 1 0 1 ~3355~1
- 5 - E 35 AND2 s 3 0 0 1 ~3355~2
- 6 - E 35 OR2 s 3 1 0 1 ~3355~3
- 7 - E 35 OR2 s 3 0 0 1 ~3355~4
- 8 - E 35 OR2 s 3 0 0 1 ~3355~5
- 1 - E 35 OR2 s 0 4 0 3 ~3355~6
- 7 - E 40 OR2 s 0 4 0 2 ~3490~1
- 8 - E 40 OR2 s 0 2 0 2 ~3490~2
- 2 - E 28 OR2 s 2 2 0 2 ~3490~3
- 2 - E 40 OR2 0 4 0 1 :3490
- 3 - E 40 OR2 0 4 0 1 :3491
- 6 - E 40 OR2 s 0 4 0 2 ~3492~1
- 2 - E 34 OR2 0 2 0 1 :3492
- 5 - E 40 OR2 0 4 0 3 :3493
- 1 - E 40 OR2 s 0 4 0 3 ~3494~1
- 5 - E 34 OR2 s 0 4 0 1 ~3522~1
- 4 - E 40 OR2 s 0 4 0 1 ~3527~1
- 7 - E 39 OR2 s 0 4 0 1 ~3528~1
- 2 - D 51 AND2 0 4 0 7 :3530
- 6 - E 31 AND2 0 4 0 1 :3538
- 4 - E 31 AND2 0 4 0 3 :3629
- 2 - E 31 AND2 s 0 3 0 2 ~3701~1
- 4 - E 44 AND2 s 0 3 0 1 ~3701~2
- 1 - E 31 OR2 s 0 4 0 1 ~3701~3
- 5 - E 44 OR2 0 4 0 1 :3701
- 5 - E 31 OR2 0 4 0 2 :3703
- 4 - E 29 OR2 0 4 0 1 :3704
- 7 - E 31 OR2 s 0 4 0 1 ~3705~1
- 3 - E 31 OR2 0 3 0 2 :3705
- 8 - E 31 OR2 0 4 0 1 :3706
- 6 - E 34 OR2 s 0 3 0 1 ~3733~1
- 8 - E 48 OR2 s 0 3 0 1 ~3735~1
- 3 - D 51 AND2 0 4 0 7 :3741
- 7 - E 30 AND2 0 4 0 4 :3840
- 1 - E 30 AND2 s 0 3 0 2 ~3912~1
- 3 - E 30 AND2 s 0 3 0 1 ~3912~2
- 2 - E 30 OR2 s 0 4 0 1 ~3912~3
- 3 - E 44 OR2 0 4 0 1 :3912
- 8 - E 30 OR2 0 4 0 2 :3914
- 6 - E 30 OR2 0 4 0 1 :3915
- 5 - E 30 OR2 s 0 4 0 2 ~3916~1
- 3 - E 48 OR2 0 2 0 1 :3916
- 7 - D 47 OR2 0 4 0 1 :3917
- 4 - E 30 OR2 s 0 4 0 1 ~3946~1
- 7 - E 34 OR2 s 0 4 0 1 ~3968~1
- 8 - E 34 OR2 0 4 1 0 :3968
- 2 - E 44 OR2 s 0 4 0 1 ~3969~1
- 6 - E 44 OR2 s 0 4 0 1 ~3969~2
- 8 - E 44 OR2 0 3 1 0 :3969
- 7 - E 48 OR2 s 0 4 0 1 ~3970~1
- 1 - E 48 OR2 0 4 1 0 :3970
- 3 - E 34 OR2 s 0 4 0 1 ~3971~1
- 4 - E 34 OR2 s 0 4 0 1 ~3971~2
- 1 - E 34 OR2 0 3 1 0 :3971
- 2 - E 29 OR2 s 0 4 0 1 ~3972~1
- 5 - E 29 OR2 s 0 4 0 1 ~3972~2
- 3 - E 29 OR2 0 3 1 0 :3972
- 5 - E 48 OR2 s 0 4 0 1 ~3973~1
- 4 - E 48 OR2 0 4 1 0 :3973
- 8 - D 47 OR2 s 0 4 0 1 ~3974~1
- 6 - D 47 OR2 0 4 1 0 :3974
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 33/208( 15%) 0/104( 0%) 14/104( 13%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
E: 22/208( 10%) 0/104( 0%) 52/104( 50%) 3/16( 18%) 7/16( 43%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 10/208( 4%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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