📄 settime2.rpt
字号:
F7 RESERVED L18 RESERVED U7 RESERVED AB18 N.C.
F8 RESERVED L19 RESERVED U8 RESERVED AB19 N.C.
F9 RESERVED L20 RESERVED U9 RESERVED AB20 N.C.
F10 GND L21 RESERVED U10 RESERVED AB21 RESERVED
F11 RESERVED L22 RESERVED U11 RESERVED AB22 RESERVED
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
D29 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
D30 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
D31 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 3/26( 11%)
D32 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 8/26( 30%)
D35 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 12/26( 46%)
D37 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/26( 34%)
D43 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
D45 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/26( 42%)
D47 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 14/26( 53%)
D49 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
D51 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 0/2 0/2 4/26( 15%)
E27 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 11/26( 42%)
E28 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
E29 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
E30 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 5/26( 19%)
E31 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 4/26( 15%)
E32 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/26( 26%)
E33 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/26( 26%)
E34 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
E35 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/26( 23%)
E37 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/26( 19%)
E39 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%)
E40 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/26( 42%)
E42 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/26( 42%)
E44 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 20/26( 76%)
E48 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 16/26( 61%)
E49 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
E50 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/26( 7%)
E51 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 13/26( 50%)
J37 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/26( 19%)
J42 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 7/26( 26%)
J43 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 1/26( 3%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 28/327 ( 8%)
Total logic cells used: 218/4992 ( 4%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 783/19968 ( 3%)
Total input pins required: 13
Total input I/O cell registers required: 0
Total output pins required: 21
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 218
Total flipflops required: 17
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 123/4992 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 8 8 0 0 8 0 8 0 0 0 0 0 8 0 8 0 8 0 1 0 8 0 74/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 5 8 8 8 8 8 8 0 3 0 1 8 0 8 0 7 0 0 0 8 8 2 8 0 121/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 23/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 16 16 16 8 8 16 0 18 0 1 8 0 16 16 7 8 0 8 8 9 2 16 0 218/0
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
L7 - - E -- INPUT ^ 0 0 0 3 d_second0
K5 - - E -- INPUT ^ 0 0 0 21 d_second1
V11 - - - -- INPUT ^ 0 0 0 21 d_second2
P11 - - - -- INPUT ^ 0 0 0 25 d_second3
E12 - - - -- INPUT ^ 0 0 0 22 d_second4
R12 - - - -- INPUT ^ 0 0 0 22 d_second5
H11 - - - -- INPUT ^ 0 0 0 21 d_second6
K4 - - E -- INPUT ^ 0 0 0 11 d_second7
D12 - - - -- INPUT G ^ 0 0 0 0 t_clk
K7 - - D -- INPUT ^ 0 0 0 6 t_sw0
J5 - - D -- INPUT ^ 0 0 0 4 t_sw1
J3 - - D -- INPUT ^ 0 0 0 6 t_sw2
K8 - - D -- INPUT ^ 0 0 0 4 t_sw3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
E15 - - - 40 OUTPUT 0 0 0 0 display_time0
J22 - - D -- OUTPUT 0 1 0 0 display_time1
J17 - - E -- OUTPUT 0 1 0 0 display_time2
K21 - - E -- OUTPUT 0 1 0 0 display_time3
K18 - - E -- OUTPUT 0 1 0 0 display_time4
K6 - - E -- OUTPUT 0 1 0 0 display_time5
J16 - - E -- OUTPUT 0 1 0 0 display_time6
K22 - - E -- OUTPUT 0 1 0 0 display_time7
K19 - - D -- OUTPUT 0 1 0 0 t_diswork
D16 - - - 42 OUTPUT 0 1 0 0 t_scan0
E16 - - - 41 OUTPUT 0 1 0 0 t_scan1
K17 - - D -- OUTPUT 0 1 0 0 t_scan2
F14 - - - 38 OUTPUT 0 1 0 0 t_scan3
H16 - - E -- OUTPUT 0 1 0 0 t_sec0
J19 - - D -- OUTPUT 0 1 0 0 t_sec1
R20 - - J -- OUTPUT 0 1 0 0 t_sec2
D21 - - A -- OUTPUT 0 1 0 0 t_sec3
D14 - - - 35 OUTPUT 0 1 0 0 t_sec4
U14 - - - 35 OUTPUT 0 1 0 0 t_sec5
Y13 - - - 31 OUTPUT 0 1 0 0 t_sec6
AA18 - - - 48 OUTPUT 0 1 0 0 t_sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\settime2.rpt
settime2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - J 43 DFFE + 0 3 0 10 t_round3 (:39)
- 1 - J 43 DFFE + 0 2 0 10 t_round2 (:40)
- 1 - J 37 DFFE + 0 1 0 12 t_round1 (:41)
- 6 - J 43 DFFE + 0 0 0 5 t_round0 (:42)
- 8 - J 43 AND2 0 4 0 1 :169
- 7 - J 43 AND2 0 4 0 1 :178
- 6 - J 42 OR2 s 0 2 0 1 ~201~1
- 3 - J 42 AND2 s 0 4 0 3 ~201~2
- 3 - J 37 AND2 ! 0 2 0 2 :201
- 2 - J 43 OR2 s ! 0 3 0 2 ~207~1
- 5 - J 43 OR2 s 0 4 0 1 ~207~2
- 5 - J 37 OR2 s ! 0 3 0 2 ~210~1
- 6 - J 37 OR2 s ! 0 3 0 3 ~210~2
- 7 - J 42 OR2 s 0 2 0 1 ~210~3
- 7 - J 37 OR2 s 0 3 0 1 ~210~4
- 4 - J 43 OR2 s ! 0 3 0 3 ~213~1
- 8 - J 42 OR2 s 0 3 0 1 ~213~2
- 4 - J 42 AND2 s ! 0 2 0 2 ~216~1
- 5 - J 42 OR2 s ! 0 3 0 2 ~216~2
- 4 - J 37 DFFE + 0 3 1 8 :219
- 2 - J 37 DFFE + 0 3 1 8 :220
- 1 - J 42 DFFE + 0 3 1 8 :221
- 2 - J 42 DFFE + 0 3 1 8 :222
- 1 - D 45 OR2 s 0 3 0 3 ~223~1
- 8 - D 45 AND2 s 0 2 0 3 ~223~2
- 5 - D 51 OR2 ! 0 4 0 11 :223
- 4 - D 31 OR2 1 2 0 1 :275
- 5 - D 31 OR2 1 2 0 2 :276
- 7 - D 43 AND2 s 0 3 0 1 ~286~1
- 7 - D 51 OR2 ! 0 4 0 17 :286
- 1 - D 31 OR2 1 2 0 1 :338
- 2 - D 31 OR2 1 2 0 3 :339
- 8 - D 31 OR2 s 0 4 0 1 ~359~1
- 6 - D 31 OR2 0 3 0 9 :359
- 7 - D 31 DFFE + 0 1 1 24 :361
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -