counter.v

Traffic light written with Verilog

`define CLOCK 16'd20000

module Counter( clk, discount, need_sec, rest_sec );
//					 switch    
input clk, discount; 

input [7:0] need_sec;

output [7:0] rest_sec;
reg [7:0] rest_sec;



reg enable;
wire [15:0] add;
Adder adder1( clk, enable, add );


reg first;

always @(posedge clk)
 begin
	if ( discount==0 )
	 begin
		if ( first==0 )
			rest_sec = need_sec;
		first=1;
	// do nothing if add!= CLOCK and rest_sec==0
		if ( add==`CLOCK )
		 begin 
			enable=0;
			rest_sec = rest_sec-1;
			if( rest_sec==0 )
				first=0;
		 end
		else if( rest_sec!=0 )
			enable=1;
	 end
	else
	 begin
		first=0;
		enable=0;
	 end
 end
endmodule


module Adder( mclk, en, count );
input mclk, en;
output [15:0] count;
reg [15:0] count;

always @(posedge mclk)
	if( en==0 )
		count=0;
	else
		count = count+1;
endmodule