switch.v

Traffic light written with Verilog

//as switch==1, stop counter
//and then as switch goes from 1 to 0,  change the state


module Switch( s_clk, s_sw, s_diswork, s_change );
input s_clk, s_sw;
output s_diswork, s_change;
reg s_diswork, s_change;

always @( posedge s_clk )
 begin
	if( (s_sw==0) && (s_diswork==1) )
		s_change=1;
	else
		s_change=0;

	if( s_sw==1 )
		s_diswork=1;
	else
		s_diswork=0;

 end
endmodule