test.map.rpt

uart 通用异步接受机 编译环境为quartus

+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |test                      ; 88         ; 32   ; |test               ;
;    |uart:inst1|            ; 34         ; 0    ; |test|uart:inst1    ;
;    |uart:inst|             ; 52         ; 0    ; |test|uart:inst     ;
+----------------------------+------------+------+---------------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; uart:inst|txhold[0]                           ;   ;
; uart:inst|txhold[1]                           ;   ;
; uart:inst|txhold[2]                           ;   ;
; uart:inst|txhold[3]                           ;   ;
; uart:inst|txhold[4]                           ;   ;
; uart:inst|txhold[5]                           ;   ;
; uart:inst|txhold[6]                           ;   ;
; uart:inst|txhold[7]                           ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Projects/Verilog HDL/uart2/test.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Dec 02 13:29:51 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Info: Found 1 design units, including 1 entities, in source file uart.v
    Info: Found entity 1: uart
Info: Found 1 design units, including 1 entities, in source file test.bdf
    Info: Found entity 1: test
Info: Elaborating entity "test" for the top level hierarchy
Warning: Port "write" of type uart and instance "inst1" is missing source signal
Warning: Port "read" of type uart and instance "inst" is missing source signal
Warning: Port "data" of type uart and instance "inst1" is missing source signal
Info: Elaborating entity "uart" for hierarchy "uart:inst1"
Warning: Reduced register "uart:inst|rd1" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|wr1" with stuck data_in port to stuck value GND
Warning: LATCH primitive "uart:inst1|txhold[0]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[1]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[2]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[3]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[4]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[5]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[6]" is permanently disabled
Warning: LATCH primitive "uart:inst1|txhold[7]" is permanently disabled
Warning: Reduced register "uart:inst1|wr2" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txdatardy" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txtag2" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txtag1" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart:inst1|txreg[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "uart:inst1|tx" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "uart:inst1|tx" with stuck data_in port to stuck value VCC
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[0]~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[1]~1 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[2]~2 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[3]~3 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[4]~4 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[5]~5 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[6]~6 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst|data[7]~7 that it feeds
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~8 to tri-state bus uart:inst|data[0]~0
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~9 to tri-state bus uart:inst|data[1]~1
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~10 to tri-state bus uart:inst|data[2]~2
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~11 to tri-state bus uart:inst|data[3]~3
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~12 to tri-state bus uart:inst|data[4]~4
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~13 to tri-state bus uart:inst|data[5]~5
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~14 to tri-state bus uart:inst|data[6]~6
Warning: Removed fan-in from always-disabled I/O buffer uart:inst|data~15 to tri-state bus uart:inst|data[7]~7
Warning: Removed always-enabled tri-state buffer uart:inst|data[0]~24 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[1]~25 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[2]~26 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[3]~27 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[4]~28 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[5]~29 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[6]~30 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer uart:inst|data[7]~31 feeding logic, open-drain buffer or output pin
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "pin_name18" stuck at VCC
    Warning: Pin "pin_name22" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted output enable signal driven by pin "RD" to global output enable signal
Info: Implemented 120 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 19 output pins
    Info: Implemented 88 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 53 warnings
    Info: Processing ended: Fri Dec 02 13:29:55 2005
    Info: Elapsed time: 00:00:04