test.map.eqn

uart 通用异步接受机 编译环境为quartus

B2_rxcnt[2]_p1_out = !B2_rxidle & B2_rxcnt[3];
B2_rxcnt[2]_p2_out = B2_rxcnt[3] & B2_hunt;
B2_rxcnt[2]_p3_out = B2_rxidle & !B2_hunt & B2_rxcnt[2];
B2_rxcnt[2]_or_out = B2_rxcnt[2]_p1_out # B2_rxcnt[2]_p2_out # B2_rxcnt[2]_p3_out;
B2_rxcnt[2]_reg_input = B2_rxcnt[2]_or_out;
B2_rxcnt[2] = TFFE(B2_rxcnt[2]_reg_input, GLOBAL(clk), , , );


--B2_rxcnt[1] is uart:inst1|rxcnt[1]
B2_rxcnt[1]_p1_out = !B2_rxidle & B2_rxcnt[2] & B2_rxcnt[3];
B2_rxcnt[1]_p2_out = B2_rxcnt[2] & B2_rxcnt[3] & B2_hunt;
B2_rxcnt[1]_p3_out = B2_rxidle & !B2_hunt & B2_rxcnt[1];
B2_rxcnt[1]_or_out = B2_rxcnt[1]_p1_out # B2_rxcnt[1]_p2_out # B2_rxcnt[1]_p3_out;
B2_rxcnt[1]_reg_input = B2_rxcnt[1]_or_out;
B2_rxcnt[1] = TFFE(B2_rxcnt[1]_reg_input, GLOBAL(clk), , , );


--B2_rxcnt[0] is uart:inst1|rxcnt[0]
B2_rxcnt[0]_p1_out = !B2_rxidle & B2_rxcnt[1] & B2_rxcnt[2] & B2_rxcnt[3];
B2_rxcnt[0]_p2_out = B2_rxcnt[1] & B2_rxcnt[2] & B2_rxcnt[3] & B2_hunt;
B2_rxcnt[0]_p3_out = B2_rxidle & !B2_hunt & B2_rxcnt[0];
B2_rxcnt[0]_or_out = B2_rxcnt[0]_p1_out # B2_rxcnt[0]_p2_out # B2_rxcnt[0]_p3_out;
B2_rxcnt[0]_reg_input = B2_rxcnt[0]_or_out;
B2_rxcnt[0] = TFFE(B2_rxcnt[0]_reg_input, GLOBAL(clk), , , );


--B2_rxclk is uart:inst1|rxclk
B2_rxclk_or_out = B2_rxcnt[0];
B2_rxclk_reg_input = B2_rxclk_or_out;
B2_rxclk = DFFE(B2_rxclk_reg_input, GLOBAL(clk), , , );


--B2_rxparity is uart:inst1|rxparity
B2_rxparity_p1_out = !B2_rxstop & !B2_rxidle;
B2_rxparity_or_out = B2_rxparity_p1_out;
B2_rxparity_reg_input = !(B2_rxparity_or_out);
B2_rxparity = DFFE(B2_rxparity_reg_input, B2_rxclk, , , );


--B2_rxreg[7] is uart:inst1|rxreg[7]
B2_rxreg[7]_p1_out = !B2_rxidle & !B2_rxparity;
B2_rxreg[7]_or_out = B2_rxreg[7]_p1_out;
B2_rxreg[7]_reg_input = !(B2_rxreg[7]_or_out);
B2_rxreg[7] = DFFE(B2_rxreg[7]_reg_input, B2_rxclk, , , );


--B2_rxreg[6] is uart:inst1|rxreg[6]
B2_rxreg[6]_p1_out = !B2_rxidle & !B2_rxreg[7];
B2_rxreg[6]_or_out = B2_rxreg[6]_p1_out;
B2_rxreg[6]_reg_input = !(B2_rxreg[6]_or_out);
B2_rxreg[6] = DFFE(B2_rxreg[6]_reg_input, B2_rxclk, , , );


--B2_rxreg[5] is uart:inst1|rxreg[5]
B2_rxreg[5]_p1_out = !B2_rxidle & !B2_rxreg[6];
B2_rxreg[5]_or_out = B2_rxreg[5]_p1_out;
B2_rxreg[5]_reg_input = !(B2_rxreg[5]_or_out);
B2_rxreg[5] = DFFE(B2_rxreg[5]_reg_input, B2_rxclk, , , );


--B2_rxreg[4] is uart:inst1|rxreg[4]
B2_rxreg[4]_p1_out = !B2_rxidle & !B2_rxreg[5];
B2_rxreg[4]_or_out = B2_rxreg[4]_p1_out;
B2_rxreg[4]_reg_input = !(B2_rxreg[4]_or_out);
B2_rxreg[4] = DFFE(B2_rxreg[4]_reg_input, B2_rxclk, , , );


--B2_rxreg[3] is uart:inst1|rxreg[3]
B2_rxreg[3]_p1_out = !B2_rxidle & !B2_rxreg[4];
B2_rxreg[3]_or_out = B2_rxreg[3]_p1_out;
B2_rxreg[3]_reg_input = !(B2_rxreg[3]_or_out);
B2_rxreg[3] = DFFE(B2_rxreg[3]_reg_input, B2_rxclk, , , );


--B2_rxreg[2] is uart:inst1|rxreg[2]
B2_rxreg[2]_p1_out = !B2_rxidle & !B2_rxreg[3];
B2_rxreg[2]_or_out = B2_rxreg[2]_p1_out;
B2_rxreg[2]_reg_input = !(B2_rxreg[2]_or_out);
B2_rxreg[2] = DFFE(B2_rxreg[2]_reg_input, B2_rxclk, , , );


--B2_rxreg[1] is uart:inst1|rxreg[1]
B2_rxreg[1]_p1_out = !B2_rxidle & !B2_rxreg[2];
B2_rxreg[1]_or_out = B2_rxreg[1]_p1_out;
B2_rxreg[1]_reg_input = !(B2_rxreg[1]_or_out);
B2_rxreg[1] = DFFE(B2_rxreg[1]_reg_input, B2_rxclk, , , );


--B2_rxreg[0] is uart:inst1|rxreg[0]
B2_rxreg[0]_p1_out = !B2_rxidle & !B2_rxreg[1];
B2_rxreg[0]_or_out = B2_rxreg[0]_p1_out;
B2_rxreg[0]_reg_input = !(B2_rxreg[0]_or_out);
B2_rxreg[0] = DFFE(B2_rxreg[0]_reg_input, B2_rxclk, , , );


--B2_rxidle is uart:inst1|rxidle
B2_rxidle_p1_out = !B2_rxidle & !B2_rxreg[0];
B2_rxidle_or_out = B2_rxidle_p1_out;
B2_rxidle_reg_input = B2_rxidle_or_out;
B2_rxidle = DFFE(B2_rxidle_reg_input, B2_rxclk, !RESET, , );


--B2_rxidle1 is uart:inst1|rxidle1
B2_rxidle1_or_out = B2_rxidle;
B2_rxidle1_reg_input = B2_rxidle1_or_out;
B2_rxidle1 = DFFE(B2_rxidle1_reg_input, GLOBAL(clk), , , );


--B2_rxstop is uart:inst1|rxstop
B2_rxstop_p1_out = !B2_rxidle & B1_tx;
B2_rxstop_or_out = B2_rxstop_p1_out;
B2_rxstop_reg_input = B2_rxstop_or_out;
B2_rxstop = DFFE(B2_rxstop_reg_input, B2_rxclk, , , );


--B2_paritygen is uart:inst1|paritygen
B2_paritygen_p1_out = B2_rxstop & !B2_paritygen;
B2_paritygen_p2_out = !B2_rxstop & B2_paritygen;
B2_paritygen_or_out = B2_paritygen_p1_out # B2_paritygen_p2_out # B2_rxidle;
B2_paritygen_reg_input = B2_paritygen_or_out;
B2_paritygen = DFFE(B2_paritygen_reg_input, B2_rxclk, , , );


--B2_rxdatardy is uart:inst1|rxdatardy
B2_rxdatardy_p1_out = B2_rd2 & B2_rxdatardy & !RESET;
B2_rxdatardy_p2_out = B2_rd2 & !RESET & B2_rxidle & !B2_rxidle1;
B2_rxdatardy_p3_out = B2_rxdatardy & !RESET & !B2_rd1;
B2_rxdatardy_p4_out = !RESET & B2_rxidle & !B2_rxidle1 & !B2_rd1;
B2_rxdatardy_or_out = B2_rxdatardy_p1_out # B2_rxdatardy_p2_out # B2_rxdatardy_p3_out # B2_rxdatardy_p4_out;
B2_rxdatardy_reg_input = B2_rxdatardy_or_out;
B2_rxdatardy = DFFE(B2_rxdatardy_reg_input, GLOBAL(clk), , , );


--B2_rxhold[0] is uart:inst1|rxhold[0]
B2_rxhold[0]_or_out = B2_rxreg[0];
B2_rxhold[0]_reg_input = B2_rxhold[0]_or_out;
B2_rxhold[0]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[0] = DFFE(B2_rxhold[0]_reg_input, GLOBAL(clk), , , B2_rxhold[0]_p3_out);


--B2_rxhold[1] is uart:inst1|rxhold[1]
B2_rxhold[1]_or_out = B2_rxreg[1];
B2_rxhold[1]_reg_input = B2_rxhold[1]_or_out;
B2_rxhold[1]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[1] = DFFE(B2_rxhold[1]_reg_input, GLOBAL(clk), , , B2_rxhold[1]_p3_out);


--B2_rxhold[2] is uart:inst1|rxhold[2]
B2_rxhold[2]_or_out = B2_rxreg[2];
B2_rxhold[2]_reg_input = B2_rxhold[2]_or_out;
B2_rxhold[2]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[2] = DFFE(B2_rxhold[2]_reg_input, GLOBAL(clk), , , B2_rxhold[2]_p3_out);


--B2_rxhold[3] is uart:inst1|rxhold[3]
B2_rxhold[3]_or_out = B2_rxreg[3];
B2_rxhold[3]_reg_input = B2_rxhold[3]_or_out;
B2_rxhold[3]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[3] = DFFE(B2_rxhold[3]_reg_input, GLOBAL(clk), , , B2_rxhold[3]_p3_out);


--B2_rxhold[4] is uart:inst1|rxhold[4]
B2_rxhold[4]_or_out = B2_rxreg[4];
B2_rxhold[4]_reg_input = B2_rxhold[4]_or_out;
B2_rxhold[4]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[4] = DFFE(B2_rxhold[4]_reg_input, GLOBAL(clk), , , B2_rxhold[4]_p3_out);


--B2_rxhold[5] is uart:inst1|rxhold[5]
B2_rxhold[5]_or_out = B2_rxreg[5];
B2_rxhold[5]_reg_input = B2_rxhold[5]_or_out;
B2_rxhold[5]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[5] = DFFE(B2_rxhold[5]_reg_input, GLOBAL(clk), , , B2_rxhold[5]_p3_out);


--B2_rxhold[6] is uart:inst1|rxhold[6]
B2_rxhold[6]_or_out = B2_rxreg[6];
B2_rxhold[6]_reg_input = B2_rxhold[6]_or_out;
B2_rxhold[6]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[6] = DFFE(B2_rxhold[6]_reg_input, GLOBAL(clk), , , B2_rxhold[6]_p3_out);


--B2_rxhold[7] is uart:inst1|rxhold[7]
B2_rxhold[7]_or_out = B2_rxreg[7];
B2_rxhold[7]_reg_input = B2_rxhold[7]_or_out;
B2_rxhold[7]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[7] = DFFE(B2_rxhold[7]_reg_input, GLOBAL(clk), , , B2_rxhold[7]_p3_out);


--B2_overrun is uart:inst1|overrun
B2_overrun_p1_out = !B2_rd2 & B2_rd1;
B2_overrun_p2_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_overrun_p3_out = !B2_rxidle & !B2_overrun;
B2_overrun_p4_out = B2_rxidle1 & !B2_overrun;
B2_overrun_or_out = B2_overrun_p1_out # B2_overrun_p2_out # B2_overrun_p3_out # B2_overrun_p4_out;
B2_overrun_reg_input = !(B2_overrun_or_out);
B2_overrun = DFFE(B2_overrun_reg_input, GLOBAL(clk), , , );


--B2_parityerr is uart:inst1|parityerr
B2_parityerr_p1_out = B2_rd2 & B2_paritygen & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & !B2_parityerr;
B2_parityerr_p2_out = B2_paritygen & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & !B2_parityerr & !B2_rd1;
B2_parityerr_p3_out = !B2_rd2 & B2_parityerr & B2_rd1;
B2_parityerr_p4_out = !B2_paritygen & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & B2_parityerr;
B2_parityerr_or_out = B2_parityerr_p1_out # B2_parityerr_p2_out # B2_parityerr_p3_out # B2_parityerr_p4_out;
B2_parityerr_reg_input = B2_parityerr_or_out;
B2_parityerr = TFFE(B2_parityerr_reg_input, GLOBAL(clk), , , );


--B2_framingerr is uart:inst1|framingerr
B2_framingerr_p1_out = !B2_rxstop & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & B2_rd2 & !B2_framingerr;
B2_framingerr_p2_out = !B2_rxstop & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & !B2_framingerr & !B2_rd1;
B2_framingerr_p3_out = B2_rxstop & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & B2_framingerr;
B2_framingerr_p4_out = !B2_rd2 & B2_framingerr & B2_rd1;
B2_framingerr_or_out = B2_framingerr_p1_out # B2_framingerr_p2_out # B2_framingerr_p3_out # B2_framingerr_p4_out;
B2_framingerr_reg_input = B2_framingerr_or_out;
B2_framingerr = TFFE(B2_framingerr_reg_input, GLOBAL(clk), , , );


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--clk is clk
--operation mode is input

clk = INPUT();


--RD is RD
--operation mode is input

RD = INPUT();


--WR is WR
--operation mode is input

WR = INPUT();


--RX is RX
--operation mode is input

RX = INPUT();


--RESET is RESET
--operation mode is input

RESET = INPUT();


--DATA_IN[0] is DATA_IN[0]
--operation mode is input

DATA_IN[0] = INPUT();


--DATA_IN[1] is DATA_IN[1]
--operation mode is input

DATA_IN[1] = INPUT();


--DATA_IN[2] is DATA_IN[2]
--operation mode is input

DATA_IN[2] = INPUT();


--DATA_IN[3] is DATA_IN[3]
--operation mode is input

DATA_IN[3] = INPUT();


--DATA_IN[4] is DATA_IN[4]
--operation mode is input

DATA_IN[4] = INPUT();


--DATA_IN[5] is DATA_IN[5]
--operation mode is input

DATA_IN[5] = INPUT();


--DATA_IN[6] is DATA_IN[6]
--operation mode is input

DATA_IN[6] = INPUT();


--DATA_IN[7] is DATA_IN[7]
--operation mode is input

DATA_IN[7] = INPUT();


--pin_name18 is pin_name18
--operation mode is output

pin_name18 = OUTPUT(~VCC~0);


--pin_name22 is pin_name22
--operation mode is output

pin_name22 = OUTPUT(~VCC~1);


--txdry is txdry
--operation mode is output

txdry = OUTPUT(B1_txdatardy);


--rxrdy is rxrdy
--operation mode is output

rxrdy = OUTPUT(B1_rxdatardy);


--overrun is overrun
--operation mode is output

overrun = OUTPUT(B1_overrun);


--parityerr is parityerr
--operation mode is output

parityerr = OUTPUT(B1_parityerr);


--framingerr is framingerr
--operation mode is output

framingerr = OUTPUT(B1_framingerr);


--pin_name21 is pin_name21
--operation mode is output

pin_name21 = OUTPUT(B2_rxdatardy);


--DATA_OUT[0] is DATA_OUT[0]
--operation mode is output

DATA_OUT[0]_tri_out = TRI(B2_rxhold[0], GLOBAL(RD));
DATA_OUT[0] = OUTPUT(DATA_OUT[0]_tri_out);


--DATA_OUT[1] is DATA_OUT[1]
--operation mode is output

DATA_OUT[1]_tri_out = TRI(B2_rxhold[1], GLOBAL(RD));
DATA_OUT[1] = OUTPUT(DATA_OUT[1]_tri_out);


--DATA_OUT[2] is DATA_OUT[2]
--operation mode is output

DATA_OUT[2]_tri_out = TRI(B2_rxhold[2], GLOBAL(RD));
DATA_OUT[2] = OUTPUT(DATA_OUT[2]_tri_out);


--DATA_OUT[3] is DATA_OUT[3]
--operation mode is output

DATA_OUT[3]_tri_out = TRI(B2_rxhold[3], GLOBAL(RD));
DATA_OUT[3] = OUTPUT(DATA_OUT[3]_tri_out);


--DATA_OUT[4] is DATA_OUT[4]
--operation mode is output

DATA_OUT[4]_tri_out = TRI(B2_rxhold[4], GLOBAL(RD));
DATA_OUT[4] = OUTPUT(DATA_OUT[4]_tri_out);


--DATA_OUT[5] is DATA_OUT[5]
--operation mode is output

DATA_OUT[5]_tri_out = TRI(B2_rxhold[5], GLOBAL(RD));
DATA_OUT[5] = OUTPUT(DATA_OUT[5]_tri_out);


--DATA_OUT[6] is DATA_OUT[6]
--operation mode is output

DATA_OUT[6]_tri_out = TRI(B2_rxhold[6], GLOBAL(RD));
DATA_OUT[6] = OUTPUT(DATA_OUT[6]_tri_out);


--DATA_OUT[7] is DATA_OUT[7]
--operation mode is output

DATA_OUT[7]_tri_out = TRI(B2_rxhold[7], GLOBAL(RD));
DATA_OUT[7] = OUTPUT(DATA_OUT[7]_tri_out);


--pin_name20 is pin_name20
--operation mode is output

pin_name20 = OUTPUT(B2_overrun);


--pin_name16 is pin_name16
--operation mode is output

pin_name16 = OUTPUT(B2_framingerr);


--pin_name23 is pin_name23
--operation mode is output

pin_name23 = OUTPUT(B2_parityerr);