test.map.eqn

uart 通用异步接受机 编译环境为quartus

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--B2_rd1 is uart:inst1|rd1
B2_rd1_or_out = GLOBAL(RD);
B2_rd1_reg_input = B2_rd1_or_out;
B2_rd1 = DFFE(B2_rd1_reg_input, GLOBAL(clk), , , );


--B1_cnt[0] is uart:inst|cnt[0]
B1_cnt[0]_p1_out = !RESET & !B1_cnt[0];
B1_cnt[0]_or_out = B1_cnt[0]_p1_out;
B1_cnt[0]_reg_input = B1_cnt[0]_or_out;
B1_cnt[0] = DFFE(B1_cnt[0]_reg_input, GLOBAL(clk), , , );


--B1_rx1 is uart:inst|rx1
B1_rx1_or_out = RX;
B1_rx1_reg_input = B1_rx1_or_out;
B1_rx1 = DFFE(B1_rx1_reg_input, GLOBAL(clk), , , );


--B2_rd2 is uart:inst1|rd2
B2_rd2_or_out = B2_rd1;
B2_rd2_reg_input = B2_rd2_or_out;
B2_rd2 = DFFE(B2_rd2_reg_input, GLOBAL(clk), , , );


--B1_cnt[1] is uart:inst|cnt[1]
B1_cnt[1]_p1_out = !RESET & B1_cnt[1] & !B1_cnt[0];
B1_cnt[1]_p2_out = !RESET & !B1_cnt[1] & B1_cnt[0];
B1_cnt[1]_or_out = B1_cnt[1]_p1_out # B1_cnt[1]_p2_out;
B1_cnt[1]_reg_input = B1_cnt[1]_or_out;
B1_cnt[1] = DFFE(B1_cnt[1]_reg_input, GLOBAL(clk), , , );


--B1_hunt is uart:inst|hunt
B1_hunt_p1_out = !RESET & B1_rxidle & !RX & B1_hunt;
B1_hunt_p2_out = !RESET & B1_rxidle & !RX & B1_rx1;
B1_hunt_or_out = B1_hunt_p1_out # B1_hunt_p2_out;
B1_hunt_reg_input = B1_hunt_or_out;
B1_hunt = DFFE(B1_hunt_reg_input, GLOBAL(clk), , , );


--B1_rxcnt[3] is uart:inst|rxcnt[3]
B1_rxcnt[3]_p1_out = B1_rxidle & !B1_hunt & B1_rxcnt[3];
B1_rxcnt[3]_or_out = B1_rxcnt[3]_p1_out;
B1_rxcnt[3]_reg_input = !B1_rxcnt[3]_or_out;
B1_rxcnt[3] = TFFE(B1_rxcnt[3]_reg_input, GLOBAL(clk), , , );


--B1_cnt[2] is uart:inst|cnt[2]
B1_cnt[2]_p1_out = !RESET & B1_cnt[1] & B1_cnt[0];
B1_cnt[2]_p2_out = RESET & B1_cnt[2];
B1_cnt[2]_or_out = B1_cnt[2]_p1_out # B1_cnt[2]_p2_out;
B1_cnt[2]_reg_input = B1_cnt[2]_or_out;
B1_cnt[2] = TFFE(B1_cnt[2]_reg_input, GLOBAL(clk), , , );


--B1_wr1 is uart:inst|wr1
B1_wr1_or_out = WR;
B1_wr1_reg_input = B1_wr1_or_out;
B1_wr1 = DFFE(B1_wr1_reg_input, GLOBAL(clk), , , );


--B1_wr2 is uart:inst|wr2
B1_wr2_or_out = B1_wr1;
B1_wr2_reg_input = B1_wr2_or_out;
B1_wr2 = DFFE(B1_wr2_reg_input, GLOBAL(clk), , , );


--B1_rxcnt[2] is uart:inst|rxcnt[2]
B1_rxcnt[2]_p1_out = !B1_rxidle & B1_rxcnt[3];
B1_rxcnt[2]_p2_out = B1_rxcnt[3] & B1_hunt;
B1_rxcnt[2]_p3_out = B1_rxidle & !B1_hunt & B1_rxcnt[2];
B1_rxcnt[2]_or_out = B1_rxcnt[2]_p1_out # B1_rxcnt[2]_p2_out # B1_rxcnt[2]_p3_out;
B1_rxcnt[2]_reg_input = B1_rxcnt[2]_or_out;
B1_rxcnt[2] = TFFE(B1_rxcnt[2]_reg_input, GLOBAL(clk), , , );


--B1L53 is uart:inst|txhold[0]~66
B1L53_p1_out = DATA_IN[0] & WR;
B1L53_p2_out = !WR & B1L53;
B1L53_p3_out = DATA_IN[0] & B1L53;
B1L53_or_out = B1L53_p1_out # B1L53_p2_out # B1L53_p3_out;
B1L53 = B1L53_or_out;


--B1L63 is uart:inst|txhold[1]~70
B1L63_p1_out = DATA_IN[1] & WR;
B1L63_p2_out = !WR & B1L63;
B1L63_p3_out = DATA_IN[1] & B1L63;
B1L63_or_out = B1L63_p1_out # B1L63_p2_out # B1L63_p3_out;
B1L63 = B1L63_or_out;


--B1L73 is uart:inst|txhold[2]~74
B1L73_p1_out = DATA_IN[2] & WR;
B1L73_p2_out = !WR & B1L73;
B1L73_p3_out = DATA_IN[2] & B1L73;
B1L73_or_out = B1L73_p1_out # B1L73_p2_out # B1L73_p3_out;
B1L73 = B1L73_or_out;


--B1L83 is uart:inst|txhold[3]~78
B1L83_p1_out = DATA_IN[3] & WR;
B1L83_p2_out = !WR & B1L83;
B1L83_p3_out = DATA_IN[3] & B1L83;
B1L83_or_out = B1L83_p1_out # B1L83_p2_out # B1L83_p3_out;
B1L83 = B1L83_or_out;


--B1L93 is uart:inst|txhold[4]~82
B1L93_p1_out = DATA_IN[4] & WR;
B1L93_p2_out = !WR & B1L93;
B1L93_p3_out = DATA_IN[4] & B1L93;
B1L93_or_out = B1L93_p1_out # B1L93_p2_out # B1L93_p3_out;
B1L93 = B1L93_or_out;


--B1L04 is uart:inst|txhold[5]~86
B1L04_p1_out = DATA_IN[5] & WR;
B1L04_p2_out = !WR & B1L04;
B1L04_p3_out = DATA_IN[5] & B1L04;
B1L04_or_out = B1L04_p1_out # B1L04_p2_out # B1L04_p3_out;
B1L04 = B1L04_or_out;


--B1L14 is uart:inst|txhold[6]~90
B1L14_p1_out = DATA_IN[6] & WR;
B1L14_p2_out = !WR & B1L14;
B1L14_p3_out = DATA_IN[6] & B1L14;
B1L14_or_out = B1L14_p1_out # B1L14_p2_out # B1L14_p3_out;
B1L14 = B1L14_or_out;


--B1L24 is uart:inst|txhold[7]~94
B1L24_p1_out = DATA_IN[7] & WR;
B1L24_p2_out = !WR & B1L24;
B1L24_p3_out = DATA_IN[7] & B1L24;
B1L24_or_out = B1L24_p1_out # B1L24_p2_out # B1L24_p3_out;
B1L24 = B1L24_or_out;


--B1_txclk is uart:inst|txclk
B1_txclk_p1_out = RESET & B1_txclk;
B1_txclk_p2_out = !RESET & !B1_cnt[2] & !B1_cnt[1] & !B1_cnt[0];
B1_txclk_or_out = B1_txclk_p1_out # B1_txclk_p2_out;
B1_txclk_reg_input = B1_txclk_or_out;
B1_txclk = TFFE(B1_txclk_reg_input, GLOBAL(clk), , , );


--B1_txtag2 is uart:inst|txtag2
B1_txtag2_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1;
B1_txtag2_or_out = B1_txtag2_p1_out;
B1_txtag2_reg_input = B1_txtag2_or_out;
B1_txtag2 = DFFE(B1_txtag2_reg_input, B1_txclk, , , );


--B1_rxcnt[1] is uart:inst|rxcnt[1]
B1_rxcnt[1]_p1_out = !B1_rxidle & B1_rxcnt[2] & B1_rxcnt[3];
B1_rxcnt[1]_p2_out = B1_rxcnt[2] & B1_rxcnt[3] & B1_hunt;
B1_rxcnt[1]_p3_out = B1_rxidle & !B1_hunt & B1_rxcnt[1];
B1_rxcnt[1]_or_out = B1_rxcnt[1]_p1_out # B1_rxcnt[1]_p2_out # B1_rxcnt[1]_p3_out;
B1_rxcnt[1]_reg_input = B1_rxcnt[1]_or_out;
B1_rxcnt[1] = TFFE(B1_rxcnt[1]_reg_input, GLOBAL(clk), , , );


--B1_txtag1 is uart:inst|txtag1
B1_txtag1_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag1;
B1_txtag1_or_out = B1_txtag1_p1_out # B1_txtag2;
B1_txtag1_reg_input = B1_txtag1_or_out;
B1_txtag1 = DFFE(B1_txtag1_reg_input, B1_txclk, , , );


--B1_txreg[7] is uart:inst|txreg[7]
B1_txreg[7]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & B1L24;
B1_txreg[7]_or_out = B1_txreg[7]_p1_out # B1_txtag1;
B1_txreg[7]_reg_input = B1_txreg[7]_or_out;
B1_txreg[7] = DFFE(B1_txreg[7]_reg_input, B1_txclk, , , );


--B1_rxcnt[0] is uart:inst|rxcnt[0]
B1_rxcnt[0]_p1_out = !B1_rxidle & B1_rxcnt[1] & B1_rxcnt[2] & B1_rxcnt[3];
B1_rxcnt[0]_p2_out = B1_rxcnt[1] & B1_rxcnt[2] & B1_rxcnt[3] & B1_hunt;
B1_rxcnt[0]_p3_out = B1_rxidle & !B1_hunt & B1_rxcnt[0];
B1_rxcnt[0]_or_out = B1_rxcnt[0]_p1_out # B1_rxcnt[0]_p2_out # B1_rxcnt[0]_p3_out;
B1_rxcnt[0]_reg_input = B1_rxcnt[0]_or_out;
B1_rxcnt[0] = TFFE(B1_rxcnt[0]_reg_input, GLOBAL(clk), , , );


--B1_rxclk is uart:inst|rxclk
B1_rxclk_or_out = B1_rxcnt[0];
B1_rxclk_reg_input = B1_rxclk_or_out;
B1_rxclk = DFFE(B1_rxclk_reg_input, GLOBAL(clk), , , );


--B1_txreg[6] is uart:inst|txreg[6]
B1_txreg[6]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txtag2 & !B1_txtag1 & B1L14;
B1_txreg[6]_or_out = B1_txreg[6]_p1_out # B1_txreg[7];
B1_txreg[6]_reg_input = B1_txreg[6]_or_out;
B1_txreg[6] = DFFE(B1_txreg[6]_reg_input, B1_txclk, , , );


--B1_rxstop is uart:inst|rxstop
B1_rxstop_p1_out = !B1_rxidle & RX;
B1_rxstop_or_out = B1_rxstop_p1_out;
B1_rxstop_reg_input = B1_rxstop_or_out;
B1_rxstop = DFFE(B1_rxstop_reg_input, B1_rxclk, , , );


--B1_txreg[5] is uart:inst|txreg[5]
B1_txreg[5]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & B1L04;
B1_txreg[5]_or_out = B1_txreg[5]_p1_out # B1_txreg[6];
B1_txreg[5]_reg_input = B1_txreg[5]_or_out;
B1_txreg[5] = DFFE(B1_txreg[5]_reg_input, B1_txclk, , , );


--B1_rxparity is uart:inst|rxparity
B1_rxparity_p1_out = !B1_rxidle & !B1_rxstop;
B1_rxparity_or_out = B1_rxparity_p1_out;
B1_rxparity_reg_input = !(B1_rxparity_or_out);
B1_rxparity = DFFE(B1_rxparity_reg_input, B1_rxclk, , , );


--B1_txreg[4] is uart:inst|txreg[4]
B1_txreg[4]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & B1L93;
B1_txreg[4]_or_out = B1_txreg[4]_p1_out # B1_txreg[5];
B1_txreg[4]_reg_input = B1_txreg[4]_or_out;
B1_txreg[4] = DFFE(B1_txreg[4]_reg_input, B1_txclk, , , );


--B1_rxreg[7] is uart:inst|rxreg[7]
B1_rxreg[7]_p1_out = !B1_rxidle & !B1_rxparity;
B1_rxreg[7]_or_out = B1_rxreg[7]_p1_out;
B1_rxreg[7]_reg_input = !(B1_rxreg[7]_or_out);
B1_rxreg[7] = DFFE(B1_rxreg[7]_reg_input, B1_rxclk, , , );


--B1_txreg[3] is uart:inst|txreg[3]
B1_txreg[3]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & B1L83;
B1_txreg[3]_or_out = B1_txreg[3]_p1_out # B1_txreg[4];
B1_txreg[3]_reg_input = B1_txreg[3]_or_out;
B1_txreg[3] = DFFE(B1_txreg[3]_reg_input, B1_txclk, , , );


--B1_rxreg[6] is uart:inst|rxreg[6]
B1_rxreg[6]_p1_out = !B1_rxidle & !B1_rxreg[7];
B1_rxreg[6]_or_out = B1_rxreg[6]_p1_out;
B1_rxreg[6]_reg_input = !(B1_rxreg[6]_or_out);
B1_rxreg[6] = DFFE(B1_rxreg[6]_reg_input, B1_rxclk, , , );


--B1_txreg[2] is uart:inst|txreg[2]
B1_txreg[2]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & B1L73;
B1_txreg[2]_or_out = B1_txreg[2]_p1_out # B1_txreg[3];
B1_txreg[2]_reg_input = B1_txreg[2]_or_out;
B1_txreg[2] = DFFE(B1_txreg[2]_reg_input, B1_txclk, , , );


--B1_rxreg[5] is uart:inst|rxreg[5]
B1_rxreg[5]_p1_out = !B1_rxidle & !B1_rxreg[6];
B1_rxreg[5]_or_out = B1_rxreg[5]_p1_out;
B1_rxreg[5]_reg_input = !(B1_rxreg[5]_or_out);
B1_rxreg[5] = DFFE(B1_rxreg[5]_reg_input, B1_rxclk, , , );


--B1_txreg[1] is uart:inst|txreg[1]
B1_txreg[1]_p1_out = !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & B1L63;
B1_txreg[1]_or_out = B1_txreg[1]_p1_out # B1_txreg[2];
B1_txreg[1]_reg_input = B1_txreg[1]_or_out;
B1_txreg[1] = DFFE(B1_txreg[1]_reg_input, B1_txclk, , , );


--B1_rxreg[4] is uart:inst|rxreg[4]
B1_rxreg[4]_p1_out = !B1_rxidle & !B1_rxreg[5];
B1_rxreg[4]_or_out = B1_rxreg[4]_p1_out;
B1_rxreg[4]_reg_input = !(B1_rxreg[4]_or_out);
B1_rxreg[4] = DFFE(B1_rxreg[4]_reg_input, B1_rxclk, , , );


--B1_txreg[0] is uart:inst|txreg[0]
B1_txreg[0]_p1_out = B1L53 & !B1_txdatardy & !B1_txreg[0] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1;
B1_txreg[0]_or_out = B1_txreg[0]_p1_out # B1_txreg[1];
B1_txreg[0]_reg_input = B1_txreg[0]_or_out;
B1_txreg[0] = DFFE(B1_txreg[0]_reg_input, B1_txclk, , , );


--B1_rxreg[3] is uart:inst|rxreg[3]
B1_rxreg[3]_p1_out = !B1_rxidle & !B1_rxreg[4];
B1_rxreg[3]_or_out = B1_rxreg[3]_p1_out;
B1_rxreg[3]_reg_input = !(B1_rxreg[3]_or_out);
B1_rxreg[3] = DFFE(B1_rxreg[3]_reg_input, B1_rxclk, , , );


--B1_txdone1 is uart:inst|txdone1
B1_txdone1_p1_out = !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1;
B1_txdone1_or_out = B1_txdone1_p1_out;
B1_txdone1_reg_input = B1_txdone1_or_out;
B1_txdone1 = DFFE(B1_txdone1_reg_input, GLOBAL(clk), , , );


--B1_rxreg[2] is uart:inst|rxreg[2]
B1_rxreg[2]_p1_out = !B1_rxidle & !B1_rxreg[3];
B1_rxreg[2]_or_out = B1_rxreg[2]_p1_out;
B1_rxreg[2]_reg_input = !(B1_rxreg[2]_or_out);
B1_rxreg[2] = DFFE(B1_rxreg[2]_reg_input, B1_rxclk, , , );


--B1_rxreg[1] is uart:inst|rxreg[1]
B1_rxreg[1]_p1_out = !B1_rxidle & !B1_rxreg[2];
B1_rxreg[1]_or_out = B1_rxreg[1]_p1_out;
B1_rxreg[1]_reg_input = !(B1_rxreg[1]_or_out);
B1_rxreg[1] = DFFE(B1_rxreg[1]_reg_input, B1_rxclk, , , );


--B1_rxreg[0] is uart:inst|rxreg[0]
B1_rxreg[0]_p1_out = !B1_rxidle & !B1_rxreg[1];
B1_rxreg[0]_or_out = B1_rxreg[0]_p1_out;
B1_rxreg[0]_reg_input = !(B1_rxreg[0]_or_out);
B1_rxreg[0] = DFFE(B1_rxreg[0]_reg_input, B1_rxclk, , , );


--B1_txdatardy is uart:inst|txdatardy
B1_txdatardy_p1_out = B1_wr2 & !B1_wr1 & !RESET;
B1_txdatardy_p2_out = !RESET & !B1_txdone1 & !B1_txdatardy;
B1_txdatardy_p3_out = !RESET & !B1_txdatardy & !B1_txreg[0] & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1;
B1_txdatardy_or_out = B1_txdatardy_p1_out # B1_txdatardy_p2_out # B1_txdatardy_p3_out;
B1_txdatardy_reg_input = !(B1_txdatardy_or_out);
B1_txdatardy = DFFE(B1_txdatardy_reg_input, GLOBAL(clk), , , );


--B1_rxidle is uart:inst|rxidle
B1_rxidle_p1_out = !B1_rxidle & !B1_rxreg[0];
B1_rxidle_or_out = B1_rxidle_p1_out;
B1_rxidle_reg_input = B1_rxidle_or_out;
B1_rxidle = DFFE(B1_rxidle_reg_input, B1_rxclk, !RESET, , );


--B1_txparity is uart:inst|txparity
B1_txparity_p1_out = !B1_txdatardy & !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & !B1_txparity;
B1_txparity_or_out = B1_txparity_p1_out # B1_txreg[0];
B1_txparity_reg_input = B1_txparity_or_out;
B1_txparity = TFFE(B1_txparity_reg_input, B1_txclk, , , );


--B1_rxidle1 is uart:inst|rxidle1
B1_rxidle1_or_out = B1_rxidle;
B1_rxidle1_reg_input = B1_rxidle1_or_out;
B1_rxidle1 = DFFE(B1_rxidle1_reg_input, GLOBAL(clk), , , );


--B1_paritygen is uart:inst|paritygen
B1_paritygen_p1_out = B1_paritygen & !B1_rxstop;
B1_paritygen_p2_out = !B1_paritygen & B1_rxstop;
B1_paritygen_or_out = B1_paritygen_p1_out # B1_paritygen_p2_out # B1_rxidle;
B1_paritygen_reg_input = B1_paritygen_or_out;
B1_paritygen = DFFE(B1_paritygen_reg_input, B1_rxclk, , , );


--B1_rxdatardy is uart:inst|rxdatardy
B1_rxdatardy_p1_out = !RESET & B1_rxdatardy;
B1_rxdatardy_p2_out = !RESET & B1_rxidle & !B1_rxidle1;
B1_rxdatardy_or_out = B1_rxdatardy_p1_out # B1_rxdatardy_p2_out;
B1_rxdatardy_reg_input = B1_rxdatardy_or_out;
B1_rxdatardy = DFFE(B1_rxdatardy_reg_input, GLOBAL(clk), , , );


--B1_tx is uart:inst|tx
B1_tx_p0_out = B1_txparity & B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & !B1_txreg[0];
B1_tx_p2_out = !B1_txparity & B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & B1_txreg[0];
B1_tx_p4_out = !B1_txreg[1] & !B1_txreg[2] & !B1_txreg[3] & !B1_txreg[4] & !B1_txreg[5] & !B1_txreg[6] & !B1_txreg[7] & !B1_txtag2 & !B1_txtag1 & !B1_txreg[0] & B1_txdatardy;
B1_tx_or_out = B1_tx_p0_out # B1_tx_p2_out # B1_tx_p4_out;
B1_tx_reg_input = B1_txreg[0] $ B1_tx_or_out;
B1_tx = DFFE(B1_tx_reg_input, B1_txclk, , , );


--B1_overrun is uart:inst|overrun
B1_overrun_or_out = B1_rxdatardy;
B1_overrun_reg_input = B1_overrun_or_out;
B1_overrun_p3_out = B1_rxidle & !B1_rxidle1;
B1_overrun = DFFE(B1_overrun_reg_input, GLOBAL(clk), , , B1_overrun_p3_out);


--B2_rx1 is uart:inst1|rx1
B2_rx1_or_out = B1_tx;
B2_rx1_reg_input = B2_rx1_or_out;
B2_rx1 = DFFE(B2_rx1_reg_input, GLOBAL(clk), , , );


--B1_parityerr is uart:inst|parityerr
B1_parityerr_or_out = B1_paritygen;
B1_parityerr_reg_input = B1_parityerr_or_out;
B1_parityerr_p3_out = !B1_rxdatardy & B1_rxidle & !B1_rxidle1;
B1_parityerr = DFFE(B1_parityerr_reg_input, GLOBAL(clk), , , B1_parityerr_p3_out);


--B1_framingerr is uart:inst|framingerr
B1_framingerr_or_out = !B1_rxstop;
B1_framingerr_reg_input = B1_framingerr_or_out;
B1_framingerr_p3_out = !B1_rxdatardy & B1_rxidle & !B1_rxidle1;
B1_framingerr = DFFE(B1_framingerr_reg_input, GLOBAL(clk), , , B1_framingerr_p3_out);


--B2_hunt is uart:inst1|hunt
B2_hunt_p1_out = B2_rxidle & !RESET & !B1_tx & B2_hunt;
B2_hunt_p2_out = B2_rxidle & !RESET & !B1_tx & B2_rx1;
B2_hunt_or_out = B2_hunt_p1_out # B2_hunt_p2_out;
B2_hunt_reg_input = B2_hunt_or_out;
B2_hunt = DFFE(B2_hunt_reg_input, GLOBAL(clk), , , );


--B2_rxcnt[3] is uart:inst1|rxcnt[3]
B2_rxcnt[3]_p1_out = B2_rxidle & !B2_hunt & B2_rxcnt[3];
B2_rxcnt[3]_or_out = B2_rxcnt[3]_p1_out;
B2_rxcnt[3]_reg_input = !B2_rxcnt[3]_or_out;
B2_rxcnt[3] = TFFE(B2_rxcnt[3]_reg_input, GLOBAL(clk), , , );


--B2_rxcnt[2] is uart:inst1|rxcnt[2]