📄 test.fit.eqn
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B2_rxcnt[2]_p3_out = B2_rxidle & !B2_hunt & B2_rxcnt[2];
B2_rxcnt[2]_or_out = B2_rxcnt[2]_p1_out # B2_rxcnt[2]_p2_out # B2_rxcnt[2]_p3_out;
B2_rxcnt[2]_reg_input = B2_rxcnt[2]_or_out;
B2_rxcnt[2] = TFFE(B2_rxcnt[2]_reg_input, GLOBAL(clk), , , );
--B2_rxcnt[1] is uart:inst1|rxcnt[1] at LC62
B2_rxcnt[1]_p1_out = !B2_rxidle & B2_rxcnt[2] & B2_rxcnt[3];
B2_rxcnt[1]_p2_out = B2_rxcnt[2] & B2_rxcnt[3] & B2_hunt;
B2_rxcnt[1]_p3_out = B2_rxidle & !B2_hunt & B2_rxcnt[1];
B2_rxcnt[1]_or_out = B2_rxcnt[1]_p1_out # B2_rxcnt[1]_p2_out # B2_rxcnt[1]_p3_out;
B2_rxcnt[1]_reg_input = B2_rxcnt[1]_or_out;
B2_rxcnt[1] = TFFE(B2_rxcnt[1]_reg_input, GLOBAL(clk), , , );
--B2_rxcnt[0] is uart:inst1|rxcnt[0] at LC61
B2_rxcnt[0]_p1_out = !B2_rxidle & B2_rxcnt[1] & B2_rxcnt[2] & B2_rxcnt[3];
B2_rxcnt[0]_p2_out = B2_rxcnt[1] & B2_rxcnt[2] & B2_rxcnt[3] & B2_hunt;
B2_rxcnt[0]_p3_out = B2_rxidle & !B2_hunt & B2_rxcnt[0];
B2_rxcnt[0]_or_out = B2_rxcnt[0]_p1_out # B2_rxcnt[0]_p2_out # B2_rxcnt[0]_p3_out;
B2_rxcnt[0]_reg_input = B2_rxcnt[0]_or_out;
B2_rxcnt[0] = TFFE(B2_rxcnt[0]_reg_input, GLOBAL(clk), , , );
--B2_rxclk is uart:inst1|rxclk at LC50
B2_rxclk_or_out = B2_rxcnt[0];
B2_rxclk_reg_input = B2_rxclk_or_out;
B2_rxclk = DFFE(B2_rxclk_reg_input, GLOBAL(clk), , , );
--B2_rxparity is uart:inst1|rxparity at LC26
B2_rxparity_p1_out = !B2_rxstop & !B2_rxidle;
B2_rxparity_or_out = B2_rxparity_p1_out;
B2_rxparity_reg_input = !(B2_rxparity_or_out);
B2_rxparity = DFFE(B2_rxparity_reg_input, B2_rxclk, , , );
--B2_rxreg[7] is uart:inst1|rxreg[7] at LC22
B2_rxreg[7]_p1_out = !B2_rxidle & !B2_rxparity;
B2_rxreg[7]_or_out = B2_rxreg[7]_p1_out;
B2_rxreg[7]_reg_input = !(B2_rxreg[7]_or_out);
B2_rxreg[7] = DFFE(B2_rxreg[7]_reg_input, B2_rxclk, , , );
--B2_rxreg[6] is uart:inst1|rxreg[6] at LC60
B2_rxreg[6]_p1_out = !B2_rxidle & !B2_rxreg[7];
B2_rxreg[6]_or_out = B2_rxreg[6]_p1_out;
B2_rxreg[6]_reg_input = !(B2_rxreg[6]_or_out);
B2_rxreg[6] = DFFE(B2_rxreg[6]_reg_input, B2_rxclk, , , );
--B2_rxreg[5] is uart:inst1|rxreg[5] at LC59
B2_rxreg[5]_p1_out = !B2_rxidle & !B2_rxreg[6];
B2_rxreg[5]_or_out = B2_rxreg[5]_p1_out;
B2_rxreg[5]_reg_input = !(B2_rxreg[5]_or_out);
B2_rxreg[5] = DFFE(B2_rxreg[5]_reg_input, B2_rxclk, , , );
--B2_rxreg[4] is uart:inst1|rxreg[4] at LC74
B2_rxreg[4]_p1_out = !B2_rxidle & !B2_rxreg[5];
B2_rxreg[4]_or_out = B2_rxreg[4]_p1_out;
B2_rxreg[4]_reg_input = !(B2_rxreg[4]_or_out);
B2_rxreg[4] = DFFE(B2_rxreg[4]_reg_input, B2_rxclk, , , );
--B2_rxreg[3] is uart:inst1|rxreg[3] at LC70
B2_rxreg[3]_p1_out = !B2_rxidle & !B2_rxreg[4];
B2_rxreg[3]_or_out = B2_rxreg[3]_p1_out;
B2_rxreg[3]_reg_input = !(B2_rxreg[3]_or_out);
B2_rxreg[3] = DFFE(B2_rxreg[3]_reg_input, B2_rxclk, , , );
--B2_rxreg[2] is uart:inst1|rxreg[2] at LC68
B2_rxreg[2]_p1_out = !B2_rxidle & !B2_rxreg[3];
B2_rxreg[2]_or_out = B2_rxreg[2]_p1_out;
B2_rxreg[2]_reg_input = !(B2_rxreg[2]_or_out);
B2_rxreg[2] = DFFE(B2_rxreg[2]_reg_input, B2_rxclk, , , );
--B2_rxreg[1] is uart:inst1|rxreg[1] at LC23
B2_rxreg[1]_p1_out = !B2_rxidle & !B2_rxreg[2];
B2_rxreg[1]_or_out = B2_rxreg[1]_p1_out;
B2_rxreg[1]_reg_input = !(B2_rxreg[1]_or_out);
B2_rxreg[1] = DFFE(B2_rxreg[1]_reg_input, B2_rxclk, , , );
--B2_rxreg[0] is uart:inst1|rxreg[0] at LC32
B2_rxreg[0]_p1_out = !B2_rxidle & !B2_rxreg[1];
B2_rxreg[0]_or_out = B2_rxreg[0]_p1_out;
B2_rxreg[0]_reg_input = !(B2_rxreg[0]_or_out);
B2_rxreg[0] = DFFE(B2_rxreg[0]_reg_input, B2_rxclk, , , );
--B2_rxidle is uart:inst1|rxidle at LC20
B2_rxidle_p1_out = !B2_rxidle & !B2_rxreg[0];
B2_rxidle_or_out = B2_rxidle_p1_out;
B2_rxidle_reg_input = B2_rxidle_or_out;
B2_rxidle = DFFE(B2_rxidle_reg_input, B2_rxclk, !RESET, , );
--B2_rxidle1 is uart:inst1|rxidle1 at LC18
B2_rxidle1_or_out = B2_rxidle;
B2_rxidle1_reg_input = B2_rxidle1_or_out;
B2_rxidle1 = DFFE(B2_rxidle1_reg_input, GLOBAL(clk), , , );
--B2_rxstop is uart:inst1|rxstop at LC31
B2_rxstop_p1_out = !B2_rxidle & B1_tx;
B2_rxstop_or_out = B2_rxstop_p1_out;
B2_rxstop_reg_input = B2_rxstop_or_out;
B2_rxstop = DFFE(B2_rxstop_reg_input, B2_rxclk, , , );
--B2_paritygen is uart:inst1|paritygen at LC28
B2_paritygen_p1_out = B2_rxstop & !B2_paritygen;
B2_paritygen_p2_out = !B2_rxstop & B2_paritygen;
B2_paritygen_or_out = B2_paritygen_p1_out # B2_paritygen_p2_out # B2_rxidle;
B2_paritygen_reg_input = B2_paritygen_or_out;
B2_paritygen = DFFE(B2_paritygen_reg_input, B2_rxclk, , , );
--B2_rxdatardy is uart:inst1|rxdatardy at LC17
B2_rxdatardy_p1_out = B2_rd2 & B2_rxdatardy & !RESET;
B2_rxdatardy_p2_out = B2_rd2 & !RESET & B2_rxidle & !B2_rxidle1;
B2_rxdatardy_p3_out = B2_rxdatardy & !RESET & !B2_rd1;
B2_rxdatardy_p4_out = !RESET & B2_rxidle & !B2_rxidle1 & !B2_rd1;
B2_rxdatardy_or_out = B2_rxdatardy_p1_out # B2_rxdatardy_p2_out # B2_rxdatardy_p3_out # B2_rxdatardy_p4_out;
B2_rxdatardy_reg_input = B2_rxdatardy_or_out;
B2_rxdatardy = DFFE(B2_rxdatardy_reg_input, GLOBAL(clk), , , );
--B2_rxhold[0] is uart:inst1|rxhold[0] at LC29
B2_rxhold[0]_or_out = B2_rxreg[0];
B2_rxhold[0]_reg_input = B2_rxhold[0]_or_out;
B2_rxhold[0]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[0] = DFFE(B2_rxhold[0]_reg_input, GLOBAL(clk), , , B2_rxhold[0]_p3_out);
--B2_rxhold[1] is uart:inst1|rxhold[1] at LC27
B2_rxhold[1]_or_out = B2_rxreg[1];
B2_rxhold[1]_reg_input = B2_rxhold[1]_or_out;
B2_rxhold[1]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[1] = DFFE(B2_rxhold[1]_reg_input, GLOBAL(clk), , , B2_rxhold[1]_p3_out);
--B2_rxhold[2] is uart:inst1|rxhold[2] at LC25
B2_rxhold[2]_or_out = B2_rxreg[2];
B2_rxhold[2]_reg_input = B2_rxhold[2]_or_out;
B2_rxhold[2]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[2] = DFFE(B2_rxhold[2]_reg_input, GLOBAL(clk), , , B2_rxhold[2]_p3_out);
--B2_rxhold[3] is uart:inst1|rxhold[3] at LC69
B2_rxhold[3]_or_out = B2_rxreg[3];
B2_rxhold[3]_reg_input = B2_rxhold[3]_or_out;
B2_rxhold[3]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[3] = DFFE(B2_rxhold[3]_reg_input, GLOBAL(clk), , , B2_rxhold[3]_p3_out);
--B2_rxhold[4] is uart:inst1|rxhold[4] at LC67
B2_rxhold[4]_or_out = B2_rxreg[4];
B2_rxhold[4]_reg_input = B2_rxhold[4]_or_out;
B2_rxhold[4]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[4] = DFFE(B2_rxhold[4]_reg_input, GLOBAL(clk), , , B2_rxhold[4]_p3_out);
--B2_rxhold[5] is uart:inst1|rxhold[5] at LC65
B2_rxhold[5]_or_out = B2_rxreg[5];
B2_rxhold[5]_reg_input = B2_rxhold[5]_or_out;
B2_rxhold[5]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[5] = DFFE(B2_rxhold[5]_reg_input, GLOBAL(clk), , , B2_rxhold[5]_p3_out);
--B2_rxhold[6] is uart:inst1|rxhold[6] at LC51
B2_rxhold[6]_or_out = B2_rxreg[6];
B2_rxhold[6]_reg_input = B2_rxhold[6]_or_out;
B2_rxhold[6]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[6] = DFFE(B2_rxhold[6]_reg_input, GLOBAL(clk), , , B2_rxhold[6]_p3_out);
--B2_rxhold[7] is uart:inst1|rxhold[7] at LC49
B2_rxhold[7]_or_out = B2_rxreg[7];
B2_rxhold[7]_reg_input = B2_rxhold[7]_or_out;
B2_rxhold[7]_p3_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_rxhold[7] = DFFE(B2_rxhold[7]_reg_input, GLOBAL(clk), , , B2_rxhold[7]_p3_out);
--B2_overrun is uart:inst1|overrun at LC24
B2_overrun_p1_out = !B2_rd2 & B2_rd1;
B2_overrun_p2_out = !B2_rxdatardy & B2_rxidle & !B2_rxidle1;
B2_overrun_p3_out = !B2_rxidle & !B2_overrun;
B2_overrun_p4_out = B2_rxidle1 & !B2_overrun;
B2_overrun_or_out = B2_overrun_p1_out # B2_overrun_p2_out # B2_overrun_p3_out # B2_overrun_p4_out;
B2_overrun_reg_input = !(B2_overrun_or_out);
B2_overrun = DFFE(B2_overrun_reg_input, GLOBAL(clk), , , );
--B2_parityerr is uart:inst1|parityerr at LC21
B2_parityerr_p1_out = B2_rd2 & B2_paritygen & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & !B2_parityerr;
B2_parityerr_p2_out = B2_paritygen & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & !B2_parityerr & !B2_rd1;
B2_parityerr_p3_out = !B2_rd2 & B2_parityerr & B2_rd1;
B2_parityerr_p4_out = !B2_paritygen & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & B2_parityerr;
B2_parityerr_or_out = B2_parityerr_p1_out # B2_parityerr_p2_out # B2_parityerr_p3_out # B2_parityerr_p4_out;
B2_parityerr_reg_input = B2_parityerr_or_out;
B2_parityerr = TFFE(B2_parityerr_reg_input, GLOBAL(clk), , , );
--B2_framingerr is uart:inst1|framingerr at LC19
B2_framingerr_p1_out = !B2_rxstop & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & B2_rd2 & !B2_framingerr;
B2_framingerr_p2_out = !B2_rxstop & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & !B2_framingerr & !B2_rd1;
B2_framingerr_p3_out = B2_rxstop & !B2_rxdatardy & B2_rxidle & !B2_rxidle1 & B2_framingerr;
B2_framingerr_p4_out = !B2_rd2 & B2_framingerr & B2_rd1;
B2_framingerr_or_out = B2_framingerr_p1_out # B2_framingerr_p2_out # B2_framingerr_p3_out # B2_framingerr_p4_out;
B2_framingerr_reg_input = B2_framingerr_or_out;
B2_framingerr = TFFE(B2_framingerr_reg_input, GLOBAL(clk), , , );
--~VCC~0 is ~VCC~0 at LC3
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);
--~VCC~1 is ~VCC~1 at LC35
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);
--clk is clk at PIN_83
--operation mode is input
clk = INPUT();
--RD is RD at PIN_84
--operation mode is input
RD = INPUT();
--WR is WR at PIN_52
--operation mode is input
WR = INPUT();
--RX is RX at PIN_33
--operation mode is input
RX = INPUT();
--RESET is RESET at PIN_81
--operation mode is input
RESET = INPUT();
--DATA_IN[0] is DATA_IN[0] at PIN_4
--operation mode is input
DATA_IN[0] = INPUT();
--DATA_IN[1] is DATA_IN[1] at PIN_24
--operation mode is input
DATA_IN[1] = INPUT();
--DATA_IN[2] is DATA_IN[2] at PIN_34
--operation mode is input
DATA_IN[2] = INPUT();
--DATA_IN[3] is DATA_IN[3] at PIN_60
--operation mode is input
DATA_IN[3] = INPUT();
--DATA_IN[4] is DATA_IN[4] at PIN_6
--operation mode is input
DATA_IN[4] = INPUT();
--DATA_IN[5] is DATA_IN[5] at PIN_36
--operation mode is input
DATA_IN[5] = INPUT();
--DATA_IN[6] is DATA_IN[6] at PIN_37
--operation mode is input
DATA_IN[6] = INPUT();
--DATA_IN[7] is DATA_IN[7] at PIN_28
--operation mode is input
DATA_IN[7] = INPUT();
--pin_name18 is pin_name18 at PIN_12
--operation mode is output
pin_name18 = OUTPUT(~VCC~0);
--pin_name22 is pin_name22 at PIN_31
--operation mode is output
pin_name22 = OUTPUT(~VCC~1);
--txdry is txdry at PIN_11
--operation mode is output
txdry = OUTPUT(B1_txdatardy);
--rxrdy is rxrdy at PIN_51
--operation mode is output
rxrdy = OUTPUT(B1_rxdatardy);
--overrun is overrun at PIN_50
--operation mode is output
overrun = OUTPUT(B1_overrun);
--parityerr is parityerr at PIN_49
--operation mode is output
parityerr = OUTPUT(B1_parityerr);
--framingerr is framingerr at PIN_48
--operation mode is output
framingerr = OUTPUT(B1_framingerr);
--pin_name21 is pin_name21 at PIN_22
--operation mode is output
pin_name21 = OUTPUT(B2_rxdatardy);
--DATA_OUT[0] is DATA_OUT[0] at PIN_15
--operation mode is output
DATA_OUT[0]_tri_out = TRI(B2_rxhold[0], GLOBAL(RD));
DATA_OUT[0] = OUTPUT(DATA_OUT[0]_tri_out);
--DATA_OUT[1] is DATA_OUT[1] at PIN_16
--operation mode is output
DATA_OUT[1]_tri_out = TRI(B2_rxhold[1], GLOBAL(RD));
DATA_OUT[1] = OUTPUT(DATA_OUT[1]_tri_out);
--DATA_OUT[2] is DATA_OUT[2] at PIN_17
--operation mode is output
DATA_OUT[2]_tri_out = TRI(B2_rxhold[2], GLOBAL(RD));
DATA_OUT[2] = OUTPUT(DATA_OUT[2]_tri_out);
--DATA_OUT[3] is DATA_OUT[3] at PIN_46
--operation mode is output
DATA_OUT[3]_tri_out = TRI(B2_rxhold[3], GLOBAL(RD));
DATA_OUT[3] = OUTPUT(DATA_OUT[3]_tri_out);
--DATA_OUT[4] is DATA_OUT[4] at PIN_45
--operation mode is output
DATA_OUT[4]_tri_out = TRI(B2_rxhold[4], GLOBAL(RD));
DATA_OUT[4] = OUTPUT(DATA_OUT[4]_tri_out);
--DATA_OUT[5] is DATA_OUT[5] at PIN_44
--operation mode is output
DATA_OUT[5]_tri_out = TRI(B2_rxhold[5], GLOBAL(RD));
DATA_OUT[5] = OUTPUT(DATA_OUT[5]_tri_out);
--DATA_OUT[6] is DATA_OUT[6] at PIN_40
--operation mode is output
DATA_OUT[6]_tri_out = TRI(B2_rxhold[6], GLOBAL(RD));
DATA_OUT[6] = OUTPUT(DATA_OUT[6]_tri_out);
--DATA_OUT[7] is DATA_OUT[7] at PIN_41
--operation mode is output
DATA_OUT[7]_tri_out = TRI(B2_rxhold[7], GLOBAL(RD));
DATA_OUT[7] = OUTPUT(DATA_OUT[7]_tri_out);
--pin_name20 is pin_name20 at PIN_18
--operation mode is output
pin_name20 = OUTPUT(B2_overrun);
--pin_name16 is pin_name16 at PIN_21
--operation mode is output
pin_name16 = OUTPUT(B2_framingerr);
--pin_name23 is pin_name23 at PIN_20
--operation mode is output
pin_name23 = OUTPUT(B2_parityerr);
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