test.hier_info

uart 通用异步接受机 编译环境为quartus

|test
pin_name16 <= uart:inst1.framingerr
clk => uart:inst1.clkx16
clk => uart:inst.clkx16
RD => uart:inst1.read
WR => uart:inst.write
RX => uart:inst.rx
RESET => uart:inst.reset
RESET => uart:inst1.reset
DATA_IN[7] => uart:inst.data[7]
DATA_IN[6] => uart:inst.data[6]
DATA_IN[5] => uart:inst.data[5]
DATA_IN[4] => uart:inst.data[4]
DATA_IN[3] => uart:inst.data[3]
DATA_IN[2] => uart:inst.data[2]
DATA_IN[1] => uart:inst.data[1]
DATA_IN[0] => uart:inst.data[0]
pin_name18 <= uart:inst1.tx
pin_name20 <= uart:inst1.overrun
pin_name21 <= uart:inst1.rxrdy
pin_name22 <= uart:inst1.txrdy
pin_name23 <= uart:inst1.parityerr
overrun <= uart:inst.overrun
rxrdy <= uart:inst.rxrdy
parityerr <= uart:inst.parityerr
framingerr <= uart:inst.framingerr
txdry <= uart:inst.txrdy
DATA_OUT[7] <= uart:inst1.data[7]
DATA_OUT[6] <= uart:inst1.data[6]
DATA_OUT[5] <= uart:inst1.data[5]
DATA_OUT[4] <= uart:inst1.data[4]
DATA_OUT[3] <= uart:inst1.data[3]
DATA_OUT[2] <= uart:inst1.data[2]
DATA_OUT[1] <= uart:inst1.data[1]
DATA_OUT[0] <= uart:inst1.data[0]


|test|uart:inst1
clkx16 => cnt[2].CLK
clkx16 => cnt[1].CLK
clkx16 => cnt[0].CLK
clkx16 => rxclk.CLK
clkx16 => hunt.CLK
clkx16 => rx1.CLK
clkx16 => rxcnt[0].CLK
clkx16 => rxcnt[1].CLK
clkx16 => rxcnt[2].CLK
clkx16 => rxcnt[3].CLK
clkx16 => txdatardy.CLK
clkx16 => wr2.CLK
clkx16 => wr1.CLK
clkx16 => txdone1.CLK
clkx16 => overrun~reg0.CLK
clkx16 => rxhold[0].CLK
clkx16 => rxhold[1].CLK
clkx16 => rxhold[2].CLK
clkx16 => rxhold[3].CLK
clkx16 => rxhold[4].CLK
clkx16 => rxhold[5].CLK
clkx16 => rxhold[6].CLK
clkx16 => rxhold[7].CLK
clkx16 => parityerr~reg0.CLK
clkx16 => framingerr~reg0.CLK
clkx16 => rxdatardy.CLK
clkx16 => rxidle1.CLK
clkx16 => rd2.CLK
clkx16 => rd1.CLK
clkx16 => txclk.CLK
read => data~8.OE
read => data~9.OE
read => data~10.OE
read => data~11.OE
read => data~12.OE
read => data~13.OE
read => data~14.OE
read => data~15.OE
read => rd1.DATAIN
write => txhold[0].LATCH_ENABLE
write => txhold[1].LATCH_ENABLE
write => txhold[2].LATCH_ENABLE
write => txhold[3].LATCH_ENABLE
write => txhold[4].LATCH_ENABLE
write => txhold[5].LATCH_ENABLE
write => txhold[6].LATCH_ENABLE
write => txhold[7].LATCH_ENABLE
write => wr1.DATAIN
rx => always1~0.IN0
rx => always1~4.IN0
rx => rxstop~0.DATAA
rx => rx1.DATAIN
reset => txclk~2.OUTPUTSELECT
reset => cnt~0.OUTPUTSELECT
reset => cnt~1.OUTPUTSELECT
reset => cnt~2.OUTPUTSELECT
reset => hunt~2.OUTPUTSELECT
reset => txdatardy~2.OUTPUTSELECT
reset => rxdatardy~3.OUTPUTSELECT
reset => rxidle.ACLR
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxrdy <= rxdatardy.DB_MAX_OUTPUT_PORT_TYPE
txrdy <= txrdy~0.DB_MAX_OUTPUT_PORT_TYPE
parityerr <= parityerr~reg0.DB_MAX_OUTPUT_PORT_TYPE
framingerr <= framingerr~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun <= overrun~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data~15
data[6] <= data~14
data[5] <= data~13
data[4] <= data~12
data[3] <= data~11
data[2] <= data~10
data[1] <= data~9
data[0] <= data~8


|test|uart:inst
clkx16 => cnt[2].CLK
clkx16 => cnt[1].CLK
clkx16 => cnt[0].CLK
clkx16 => rxclk.CLK
clkx16 => hunt.CLK
clkx16 => rx1.CLK
clkx16 => rxcnt[0].CLK
clkx16 => rxcnt[1].CLK
clkx16 => rxcnt[2].CLK
clkx16 => rxcnt[3].CLK
clkx16 => txdatardy.CLK
clkx16 => wr2.CLK
clkx16 => wr1.CLK
clkx16 => txdone1.CLK
clkx16 => overrun~reg0.CLK
clkx16 => rxhold[0].CLK
clkx16 => rxhold[1].CLK
clkx16 => rxhold[2].CLK
clkx16 => rxhold[3].CLK
clkx16 => rxhold[4].CLK
clkx16 => rxhold[5].CLK
clkx16 => rxhold[6].CLK
clkx16 => rxhold[7].CLK
clkx16 => parityerr~reg0.CLK
clkx16 => framingerr~reg0.CLK
clkx16 => rxdatardy.CLK
clkx16 => rxidle1.CLK
clkx16 => rd2.CLK
clkx16 => rd1.CLK
clkx16 => txclk.CLK
read => data~8.OE
read => data~9.OE
read => data~10.OE
read => data~11.OE
read => data~12.OE
read => data~13.OE
read => data~14.OE
read => data~15.OE
read => rd1.DATAIN
write => txhold[0].LATCH_ENABLE
write => txhold[1].LATCH_ENABLE
write => txhold[2].LATCH_ENABLE
write => txhold[3].LATCH_ENABLE
write => txhold[4].LATCH_ENABLE
write => txhold[5].LATCH_ENABLE
write => txhold[6].LATCH_ENABLE
write => txhold[7].LATCH_ENABLE
write => wr1.DATAIN
rx => always1~0.IN0
rx => always1~4.IN0
rx => rxstop~0.DATAA
rx => rx1.DATAIN
reset => txclk~2.OUTPUTSELECT
reset => cnt~0.OUTPUTSELECT
reset => cnt~1.OUTPUTSELECT
reset => cnt~2.OUTPUTSELECT
reset => hunt~2.OUTPUTSELECT
reset => txdatardy~2.OUTPUTSELECT
reset => rxdatardy~3.OUTPUTSELECT
reset => rxidle.ACLR
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxrdy <= rxdatardy.DB_MAX_OUTPUT_PORT_TYPE
txrdy <= txrdy~0.DB_MAX_OUTPUT_PORT_TYPE
parityerr <= parityerr~reg0.DB_MAX_OUTPUT_PORT_TYPE
framingerr <= framingerr~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun <= overrun~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data~15
data[6] <= data~14
data[5] <= data~13
data[4] <= data~12
data[3] <= data~11
data[2] <= data~10
data[1] <= data~9
data[0] <= data~8