test.map.qmsg

uart 通用异步接受机 编译环境为quartus

{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "uart:inst1\|tx High " "Info: Power-up level of register \"uart:inst1\|tx\" is not specified -- using power-up level of High to minimize register" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 23 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|tx data_in VCC " "Warning: Reduced register \"uart:inst1\|tx\" with stuck data_in port to stuck value VCC" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 23 -1 0 } }  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[0\]~0 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[0\]~0 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[1\]~1 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[1\]~1 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[2\]~2 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[2\]~2 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[3\]~3 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[3\]~3 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[4\]~4 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[4\]~4 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[5\]~5 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[5\]~5 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[6\]~6 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[6\]~6 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "uart:inst\|data\[7\]~7 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus uart:inst\|data\[7\]~7 that it feeds" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~8 uart:inst\|data\[0\]~0 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~8 to tri-state bus uart:inst\|data\[0\]~0" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~9 uart:inst\|data\[1\]~1 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~9 to tri-state bus uart:inst\|data\[1\]~1" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~10 uart:inst\|data\[2\]~2 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~10 to tri-state bus uart:inst\|data\[2\]~2" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~11 uart:inst\|data\[3\]~3 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~11 to tri-state bus uart:inst\|data\[3\]~3" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~12 uart:inst\|data\[4\]~4 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~12 to tri-state bus uart:inst\|data\[4\]~4" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~13 uart:inst\|data\[5\]~5 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~13 to tri-state bus uart:inst\|data\[5\]~5" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~14 uart:inst\|data\[6\]~6 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~14 to tri-state bus uart:inst\|data\[6\]~6" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "uart:inst\|data~15 uart:inst\|data\[7\]~7 " "Warning: Removed fan-in from always-disabled I/O buffer uart:inst\|data~15 to tri-state bus uart:inst\|data\[7\]~7" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[0\]~24 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[0\]~24 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[1\]~25 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[1\]~25 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[2\]~26 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[2\]~26 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[3\]~27 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[3\]~27 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[4\]~28 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[4\]~28 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[5\]~29 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[5\]~29 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[6\]~30 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[6\]~30 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "uart:inst\|data\[7\]~31 " "Warning: Removed always-enabled tri-state buffer uart:inst\|data\[7\]~31 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "pin_name18 VCC " "Warning: Pin \"pin_name18\" stuck at VCC" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 80 744 920 96 "pin_name18" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pin_name22 VCC " "Warning: Pin \"pin_name22\" stuck at VCC" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 112 744 920 128 "pin_name22" "" } } } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_OE" "RD " "Info: Promoted output enable signal driven by pin \"RD\" to global output enable signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "120 " "Info: Implemented 120 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "88 " "Info: Implemented 88 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 53 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 53 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 13:29:55 2005 " "Info: Processing ended: Fri Dec 02 13:29:55 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}