test.map.qmsg

uart 通用异步接受机 编译环境为quartus

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 13:29:51 2005 " "Info: Processing started: Fri Dec 02 13:29:51 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "write uart inst1 " "Warning: Port \"write\" of type uart and instance \"inst1\" is missing source signal" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 56 544 680 216 "inst1" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "read uart inst " "Warning: Port \"read\" of type uart and instance \"inst\" is missing source signal" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 56 96 232 216 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "data uart inst1 " "Warning: Port \"data\" of type uart and instance \"inst1\" is missing source signal" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 56 544 680 216 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart uart:inst1 " "Info: Elaborating entity \"uart\" for hierarchy \"uart:inst1\"" {  } { { "test.bdf" "inst1" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 56 544 680 216 "inst1" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst\|rd1 data_in GND " "Warning: Reduced register \"uart:inst\|rd1\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 216 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|wr1 data_in GND " "Warning: Reduced register \"uart:inst1\|wr1\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 197 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[0\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[0\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[1\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[1\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[2\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[2\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[3\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[3\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[4\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[4\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[5\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[5\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[6\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[6\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "uart:inst1\|txhold\[7\] " "Warning: LATCH primitive \"uart:inst1\|txhold\[7\]\" is permanently disabled" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|wr2 data_in GND " "Warning: Reduced register \"uart:inst1\|wr2\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 197 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txdatardy data_in GND " "Warning: Reduced register \"uart:inst1\|txdatardy\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 50 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txtag2 data_in GND " "Warning: Reduced register \"uart:inst1\|txtag2\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 42 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txtag1 data_in GND " "Warning: Reduced register \"uart:inst1\|txtag1\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 43 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[7\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[6\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[6\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[5\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[5\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[4\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[4\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[3\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[3\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[2\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[2\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[1\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[1\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart:inst1\|txreg\[0\] data_in GND " "Warning: Reduced register \"uart:inst1\|txreg\[0\]\" with stuck data_in port to stuck value GND" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 41 -1 0 } }  } 0}