test.tan.qmsg

uart 通用异步接受机 编译环境为quartus

{ "Info" "ITDB_TSU_RESULT" "uart:inst\|cnt\[0\] RESET clk 3.800 ns register " "Info: tsu for register \"uart:inst\|cnt\[0\]\" (data pin = \"RESET\", clock pin = \"clk\") is 3.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns + Longest pin register " "Info: + Longest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns RESET 1 PIN PIN_81 22 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 22; PIN Node = 'RESET'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { RESET } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 16 -160 8 32 "RESET" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(3.000 ns) 5.000 ns uart:inst\|cnt\[0\] 2 REG LC41 5 " "Info: 2: + IC(1.800 ns) + CELL(3.000 ns) = 5.000 ns; Loc. = LC41; Fanout = 5; REG Node = 'uart:inst\|cnt\[0\]'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.800 ns" { RESET uart:inst|cnt[0] } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 65 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 64.00 % " "Info: Total cell delay = 3.200 ns ( 64.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns 36.00 % " "Info: Total interconnect delay = 1.800 ns ( 36.00 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "5.000 ns" { RESET uart:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.000 ns" { RESET RESET~out uart:inst|cnt[0] } { 0.000ns 0.000ns 1.800ns } { 0.000ns 0.200ns 3.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 65 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns uart:inst\|cnt\[0\] 2 REG LC41 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC41; Fanout = 5; REG Node = 'uart:inst\|cnt\[0\]'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.600 ns" { clk uart:inst|cnt[0] } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 65 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst|cnt[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "5.000 ns" { RESET uart:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.000 ns" { RESET RESET~out uart:inst|cnt[0] } { 0.000ns 0.000ns 1.800ns } { 0.000ns 0.200ns 3.000ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst|cnt[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk pin_name23 uart:inst1\|parityerr 4.000 ns register " "Info: tco from clock \"clk\" to destination pin \"pin_name23\" through register \"uart:inst1\|parityerr\" is 4.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns uart:inst1\|parityerr 2 REG LC21 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC21; Fanout = 6; REG Node = 'uart:inst1\|parityerr'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.600 ns" { clk uart:inst1|parityerr } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst1|parityerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst1|parityerr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst1\|parityerr 1 REG LC21 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 6; REG Node = 'uart:inst1\|parityerr'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { uart:inst1|parityerr } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns pin_name23 2 PIN PIN_20 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'pin_name23'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.400 ns" { uart:inst1|parityerr pin_name23 } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 128 744 920 144 "pin_name23" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 100.00 % " "Info: Total cell delay = 0.400 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.400 ns" { uart:inst1|parityerr pin_name23 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.400 ns" { uart:inst1|parityerr pin_name23 } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst1|parityerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst1|parityerr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.400 ns" { uart:inst1|parityerr pin_name23 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.400 ns" { uart:inst1|parityerr pin_name23 } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "RD DATA_OUT\[7\] 6.400 ns Longest " "Info: Longest tpd from source pin \"RD\" to destination pin \"DATA_OUT\[7\]\" is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns RD 1 PIN PIN_84 9 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_84; Fanout = 9; PIN Node = 'RD'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { RD } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 96 -160 8 112 "RD" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(4.700 ns) 6.400 ns DATA_OUT\[7\] 2 PIN PIN_41 0 " "Info: 2: + IC(0.100 ns) + CELL(4.700 ns) = 6.400 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'DATA_OUT\[7\]'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.800 ns" { RD DATA_OUT[7] } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 176 744 920 192 "DATA_OUT\[0..7\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 98.44 % " "Info: Total cell delay = 6.300 ns ( 98.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 1.56 % " "Info: Total interconnect delay = 0.100 ns ( 1.56 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "6.400 ns" { RD DATA_OUT[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.400 ns" { RD RD~out DATA_OUT[7] } { 0.000ns 0.000ns 0.100ns } { 0.000ns 1.600ns 4.700ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "uart:inst\|rxstop RX clk 5.300 ns register " "Info: th for register \"uart:inst\|rxstop\" (data pin = \"RX\", clock pin = \"clk\") is 5.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns uart:inst\|rxclk 2 REG LC33 12 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC33; Fanout = 12; REG Node = 'uart:inst\|rxclk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.000 ns" { clk uart:inst|rxclk } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 8.200 ns uart:inst\|rxstop 3 REG LC36 4 " "Info: 3: + IC(1.500 ns) + CELL(3.100 ns) = 8.200 ns; Loc. = LC36; Fanout = 4; REG Node = 'uart:inst\|rxstop'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { uart:inst|rxclk uart:inst|rxstop } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 81.71 % " "Info: Total cell delay = 6.700 ns ( 81.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 18.29 % " "Info: Total interconnect delay = 1.500 ns ( 18.29 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.200 ns" { clk uart:inst|rxclk uart:inst|rxstop } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out uart:inst|rxclk uart:inst|rxstop } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns RX 1 PIN PIN_33 4 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 4; PIN Node = 'RX'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { RX } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { 128 -160 8 144 "RX" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.600 ns uart:inst\|rxstop 2 REG LC36 4 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'uart:inst\|rxstop'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.400 ns" { RX uart:inst|rxstop } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 69.57 % " "Info: Total cell delay = 3.200 ns ( 69.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 30.43 % " "Info: Total interconnect delay = 1.400 ns ( 30.43 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { RX uart:inst|rxstop } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.600 ns" { RX RX~out uart:inst|rxstop } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.200 ns" { clk uart:inst|rxclk uart:inst|rxstop } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out uart:inst|rxclk uart:inst|rxstop } { 0.000ns 0.000ns 0.000ns 1.500ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { RX uart:inst|rxstop } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.600 ns" { RX RX~out uart:inst|rxstop } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 13:30:05 2005 " "Info: Processing ended: Fri Dec 02 13:30:05 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}