test.tan.qmsg

uart 通用异步接受机 编译环境为quartus

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[0\]~66 " "Info: Node \"uart:inst\|txhold\[0\]~66\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "uart:inst1\|rxclk " "Info: Detected ripple clock \"uart:inst1\|rxclk\" as buffer" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 60 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart:inst1\|rxclk" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|txclk " "Info: Detected ripple clock \"uart:inst\|txclk\" as buffer" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 47 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart:inst\|txclk" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|rxclk " "Info: Detected ripple clock \"uart:inst\|rxclk\" as buffer" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 60 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart:inst\|rxclk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register uart:inst1\|rxidle register uart:inst1\|framingerr 76.34 MHz 13.1 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.34 MHz between source register \"uart:inst1\|rxidle\" and destination register \"uart:inst1\|framingerr\" (period= 13.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Longest register register " "Info: + Longest register to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst1\|rxidle 1 REG LC20 40 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC20; Fanout = 40; REG Node = 'uart:inst1\|rxidle'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { uart:inst1|rxidle } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 61 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.000 ns) 4.600 ns uart:inst1\|framingerr 2 REG LC19 6 " "Info: 2: + IC(1.600 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC19; Fanout = 6; REG Node = 'uart:inst1\|framingerr'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { uart:inst1|rxidle uart:inst1|framingerr } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 65.22 % " "Info: Total cell delay = 3.000 ns ( 65.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 34.78 % " "Info: Total interconnect delay = 1.600 ns ( 34.78 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { uart:inst1|rxidle uart:inst1|framingerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.600 ns" { uart:inst1|rxidle uart:inst1|framingerr } { 0.000ns 1.600ns } { 0.000ns 3.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.100 ns - Smallest " "Info: - Smallest clock skew is -6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns uart:inst1\|framingerr 2 REG LC19 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC19; Fanout = 6; REG Node = 'uart:inst1\|framingerr'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.600 ns" { clk uart:inst1|framingerr } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst1|framingerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst1|framingerr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns uart:inst1\|rxclk 2 REG LC50 12 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC50; Fanout = 12; REG Node = 'uart:inst1\|rxclk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.000 ns" { clk uart:inst1|rxclk } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 8.300 ns uart:inst1\|rxidle 3 REG LC20 40 " "Info: 3: + IC(1.600 ns) + CELL(3.100 ns) = 8.300 ns; Loc. = LC20; Fanout = 40; REG Node = 'uart:inst1\|rxidle'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.700 ns" { uart:inst1|rxclk uart:inst1|rxidle } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 61 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 80.72 % " "Info: Total cell delay = 6.700 ns ( 80.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 19.28 % " "Info: Total interconnect delay = 1.600 ns ( 19.28 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.300 ns" { clk uart:inst1|rxclk uart:inst1|rxidle } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out uart:inst1|rxclk uart:inst1|rxidle } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst1|framingerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst1|framingerr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.300 ns" { clk uart:inst1|rxclk uart:inst1|rxidle } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out uart:inst1|rxclk uart:inst1|rxidle } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 61 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 27 -1 0 } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { uart:inst1|rxidle uart:inst1|framingerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.600 ns" { uart:inst1|rxidle uart:inst1|framingerr } { 0.000ns 1.600ns } { 0.000ns 3.000ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst1|framingerr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst1|framingerr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.300 ns" { clk uart:inst1|rxclk uart:inst1|rxidle } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out uart:inst1|rxclk uart:inst1|rxidle } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "uart:inst\|txdatardy uart:inst\|txtag2 clk 1.9 ns " "Info: Found hold time violation between source  pin or register \"uart:inst\|txdatardy\" and destination pin or register \"uart:inst\|txtag2\" for clock \"clk\" (Hold time is 1.9 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.000 ns + Largest " "Info: + Largest clock skew is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns uart:inst\|txclk 2 REG LC53 14 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC53; Fanout = 14; REG Node = 'uart:inst\|txclk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.000 ns" { clk uart:inst|txclk } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 8.200 ns uart:inst\|txtag2 3 REG LC9 16 " "Info: 3: + IC(1.500 ns) + CELL(3.100 ns) = 8.200 ns; Loc. = LC9; Fanout = 16; REG Node = 'uart:inst\|txtag2'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.600 ns" { uart:inst|txclk uart:inst|txtag2 } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 81.71 % " "Info: Total cell delay = 6.700 ns ( 81.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 18.29 % " "Info: Total interconnect delay = 1.500 ns ( 18.29 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.200 ns" { clk uart:inst|txclk uart:inst|txtag2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out uart:inst|txclk uart:inst|txtag2 } { 0.0ns 0.0ns 0.0ns 1.5ns } { 0.0ns 1.6ns 2.0ns 3.1ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 42 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 42; CLK Node = 'clk'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "D:/Projects/Verilog HDL/uart2/test.bdf" { { -16 -160 8 0 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns uart:inst\|txdatardy 2 REG LC5 15 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC5; Fanout = 15; REG Node = 'uart:inst\|txdatardy'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "0.600 ns" { clk uart:inst|txdatardy } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst|txdatardy } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst|txdatardy } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.6ns 0.6ns } } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.200 ns" { clk uart:inst|txclk uart:inst|txtag2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out uart:inst|txclk uart:inst|txtag2 } { 0.0ns 0.0ns 0.0ns 1.5ns } { 0.0ns 1.6ns 2.0ns 3.1ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst|txdatardy } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst|txdatardy } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.6ns 0.6ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns - " "Info: - Micro clock to output delay of source is 1.400 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 50 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns - Shortest register register " "Info: - Shortest register to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst\|txdatardy 1 REG LC5 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 15; REG Node = 'uart:inst\|txdatardy'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "" { uart:inst|txdatardy } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.400 ns uart:inst\|txtag2 2 REG LC9 16 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.400 ns; Loc. = LC9; Fanout = 16; REG Node = 'uart:inst\|txtag2'" {  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.400 ns" { uart:inst|txdatardy uart:inst|txtag2 } "NODE_NAME" } "" } } { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 68.18 % " "Info: Total cell delay = 3.000 ns ( 68.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 31.82 % " "Info: Total interconnect delay = 1.400 ns ( 31.82 % )" {  } {  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.400 ns" { uart:inst|txdatardy uart:inst|txtag2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.400 ns" { uart:inst|txdatardy uart:inst|txtag2 } { 0.0ns 1.4ns } { 0.0ns 3.0ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 42 -1 0 } }  } 0}  } { { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "8.200 ns" { clk uart:inst|txclk uart:inst|txtag2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out uart:inst|txclk uart:inst|txtag2 } { 0.0ns 0.0ns 0.0ns 1.5ns } { 0.0ns 1.6ns 2.0ns 3.1ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "2.200 ns" { clk uart:inst|txdatardy } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.200 ns" { clk clk~out uart:inst|txdatardy } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.6ns 0.6ns } } } { "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" "" { Report "D:/Projects/Verilog HDL/uart2/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "D:/Projects/Verilog HDL/uart2/db/test.quartus_db" { Floorplan "D:/Projects/Verilog HDL/uart2/" "" "4.400 ns" { uart:inst|txdatardy uart:inst|txtag2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.400 ns" { uart:inst|txdatardy uart:inst|txtag2 } { 0.0ns 1.4ns } { 0.0ns 3.0ns } } }  } 0}