test.tan.qmsg

来自「uart 通用异步接受机 编译环境为quartus」· QMSG 代码 · 共 24 行 · 第 1/4 页

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[6\]~90 " "Info: Node \"uart:inst\|txhold\[6\]~90\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[5\]~86 " "Info: Node \"uart:inst\|txhold\[5\]~86\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[4\]~82 " "Info: Node \"uart:inst\|txhold\[4\]~82\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[3\]~78 " "Info: Node \"uart:inst\|txhold\[3\]~78\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[2\]~74 " "Info: Node \"uart:inst\|txhold\[2\]~74\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[1\]~70 " "Info: Node \"uart:inst\|txhold\[1\]~70\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}