test.tan.qmsg

uart 通用异步接受机 编译环境为quartus

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 13:30:05 2005 " "Info: Processing started: Fri Dec 02 13:30:05 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off test -c test " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test -c test" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "uart:inst\|txhold\[7\]~94 " "Info: Node \"uart:inst\|txhold\[7\]~94\"" {  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}  } { { "uart.v" "" { Text "D:/Projects/Verilog HDL/uart2/uart.v" 38 -1 0 } }  } 0}