90_wss_coprocessor.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--LIBRARY synergy;
--  USE synergy.signed_arith.all;

LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_arith.all;
--  USE ieee.std_logic_signed.all;
--  USE synergy.signed_arith.all;
  USE work.pkg_types.all;

  ENTITY co_processor IS
	PORT(	clk	: IN bit1;
		reset	: IN bit1;
		c	: IN bit8;
		s	: IN bit8;
		p_sel	: IN bit1;
		mode	: IN bit1;
		sel_read: OUT bit1;
		c_ad	: OUT bit2;
		s_ad	: OUT bit3;
		dmin	: OUT bit11;
		vector	: OUT bit4;
                done0   : OUT bit1;
                done1   : OUT bit1);
        END co_processor;

  architecture behavior OF co_processor IS
  BEGIN
      PROCESS 
       VARIABLE  i               :bit3_r;
       VARIABLE  x               :bit4_r;	
       VARIABLE  d,min           :bit11_r;

       FUNCTION dist(c,s: IN bit8;d: IN bit11_r) RETURN bit11_r IS 
       VARIABLE  val8            :bit8_r;
       VARIABLE  val11           :bit11_r;	
       BEGIN
         val8:=to_stdlogicvector(c)-to_stdlogicvector(s);
         --val8:=abs(val8);
		 if val8(7)='1'
		 then
         val8(7):='0';
		 end if;

         val11:=val8 + d;
         RETURN(val11);
       END dist;

       PROCEDURE assign(i: IN bit3_r;x: IN bit4_r;SIGNAL c_ad:OUT bit3;SIGNAL s_ad:OUT bit5) IS
       BEGIN
         c_ad <= to_stdulogicvector(i) AFTER 2 ns;
         s_ad <= to_stdulogicvector(("00"&i)+('0'&x)) AFTER 2 ns;        
       END assign;

       PROCEDURE init_min(SIGNAL dmin:OUT bit11) IS   
       BEGIN
         min := "11111111000";
         dmin <= "00000000000";
       END init_min;

       PROCEDURE sel_min(d: IN bit11_r; x: IN bit4_r;SIGNAL dmin:OUT bit11;SIGNAL vector:OUT bit4) IS
       BEGIN
       --  IF unsigned(d) <= unsigned(min)
	   IF d<min
	 THEN
            min		:= d;
            vector      <= to_stdulogicvector(x);
         END IF;
         dmin <= to_stdulogicvector(min);
       END sel_min; 
        
       BEGIN
         sel_read <= '0';
         done0 <= '1';
         done1 <= '1';

         WAIT UNTIL p_sel = '1' AND rising_edge(clk) AND reset = '1';
         
         IF mode = '0' OR reset = '0' THEN
                 i       :="000";  
                 x       :="0000";  
                 d       :="00000000000";
                 init_min(dmin);
                 vector <= "0000";
                 done0  <= '0';
         ELSE
                 IF mode = '1' THEN
                      done1<='0';
                 END IF;
         END IF;
         
         WAIT UNTIL p_sel = '0' AND rising_edge(clk) AND reset = '1';          

         loop_x: WHILE reset='1' LOOP
              d := "00000000000";  
              loop_i:WHILE reset='1' LOOP 
                     sel_read <= '1';  
                     assign(i,x,c_ad,s_ad); 
                     
		     WAIT UNTIL rising_edge(clk);   

		     sel_read <= '0';  
                     d:=dist(c,s,d);
                     i:=i+1;
                     IF i=0 THEN
                             EXIT loop_i;
                     END IF;
               END LOOP loop_i;
               sel_min(d,x,dmin,vector);
               x := x+1;
               IF(x=0 OR x=8) THEN
                      EXIT loop_x;
               END IF;
           END LOOP loop_x;       
       END PROCESS;
       END behavior;