5_mux2.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

entity bit_rtl_mux2 is port (
   in1 : in bit_vector;
   in2 : in bit_vector;
   pout : out bit_vector;
   cnt1: in bit );
end bit_rtl_mux2;

architecture func of bit_rtl_mux2 is
begin
   pout <= in1 when cnt1 ='0' else
		  in2;
end  func;