25_test_1.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Page		 	: 319 - 320
--
-- Objective 	: unexpected multisources: case 1
--
-- File Name 	: test_1a.vhd
--
-- Author    	: Joseph Pick
--

entity Test_1a is
end TEst_1a;

architecture Behave_1 of Test_1a is
	signal Sample : BIT_VECTOR ( 4 downto 0 );

begin 

		Load_N:
		process
		begin 
		for Index in 4 to 4 loop
			Sample ( Index ) <= '1';
				wait for 2 ns;
				assert FALSE
					report "Test went OK"
					severity NOTE;
		end loop;
			wait;
		end process;

		Load_M:
		process
		begin 
		for Index in 1 to 1 loop
			Sample ( Index ) <= '1';
			wait for 12 ns;
			assert FALSE 
				report "Test went OK"
				severity NOTE;
		end loop;
			wait;
	end process;

end Behave_1;