25_test_1a.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Page		 	: 318 _ 319
--
-- Objective 	: Reference for Test_1a,1b,1d, and 1e
--
-- File Name 	: test_1.vhd
--
-- Author    	: Joseph Pick
--

entity Test_1 is
end Test_1;

architecture Behave_1 of Test_1 is
	signal Sample : BIT_VECTOR ( 4 downto 0 ) := (others => '1');
begin

--	Load_N:
--	process
--	begin
		Sample(4) <= '0';
		Sample(1) <= '0';
--		wait for 2 ns;
--		 assert FALSE
--			report "Test went OK"
--			severity NOTE;
--		 wait;
--	end process;

--	Load_M:
--	process
--	begin
		--Sample(1) <= '0';
		--wait for 12 ns;
	--	assert FALSE
	--		report "Test went OK"
	--		severity NOTE;
--		wait;
--	end process;

end Behave_1;