28_test_64a.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--Page          :301

--Objective     :'TRANSACTION of formal parameters

--Filename      :test_64a.vhd

--Author        :Joseph Pick

entity Test_64a is
end Test_64a;

architecture Behave_1 of Test_64a is
 
  signal Sig_Nat : NATURAL := 0;

  procedure Set_55 ( Signal Sig_Param : in NATURAL;
						Count_Param : out NATURAL) is 
  begin 
	wait on Sig_Param'TRANSACTION;
	Count_Param := 55;
  end Set_55;

begin

  Gen_Signal:
  process
	variable Count_PS : NATURAL := 0;
  begin 
	Count_PS := Count_PS + 1;
	Set_55 (Sig_Nat, Count_PS);
	wait for 20 ns;
  end process Gen_Signal;

  Sig_Nat <= 22 after 20 ns;
end Behave_1;