15_mvl7_syn_types.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 20 行

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-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS

--  Developed on Nov 1, 1991 by :
--                                Indraneel Ghosh,
--                                CADLAB,
--                                Univ. of Calif. , Irvine.

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use work.TYPES.all;

package SYNTHESIS_TYPES is

subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);

end SYNTHESIS_TYPES;