33_comp.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--**VHDL*************************************************************
--
-- SRC-MODULE : COMP
-- NAME       : comp.vhdl
-- VERSION    : 1.0
--
-- PURPOSE    : Architecture of COMP benchmark
--
-- AUTHOR     : Yan.Zongfu
-- LAST UPDATE: Wes Nov 15 15:23:07 1995
--
--*******************************************************************
--
-- Comparate two integers
--

-- Types Package
package types is
   subtype short is integer range 0 to 255;
end types;
use work.types.all;

-- Entity declaration
entity COMP is
    port(A  	 	: in short;
		 B  	 	: in short;
		 IN_READY	: in bit;
		 OUT_REQ 	: in bit;
		 CLK	 	: in bit;
		 OUT_READY	: out bit;
         GT 	 	: out bit;
         LT 	 	: out bit;
         EQ 	 	: out bit);
end COMP;

-- The architecture body of the COMP

architecture ALGORITHM of COMP is

begin                                
	-- comparator operator
	process
	begin	

    wait until CLK'event and CLK= '1' and IN_READY = '1';

	-- compare values

	-- A > B
	if A > B then
		GT <= '1' ;
		LT <= '0' ;
		EQ <= '0' ;
	else
		-- A < B
		if A < B then
			GT <= '0' ;
			LT <= '1' ;
			EQ <= '0' ;
		
		-- A = B
		else 
			GT <= '0' ;
			LT <= '0' ;
			EQ <= '1' ;
		end if;
	end if;

    wait until CLK'event and CLK= '1' and OUT_REQ = '1';
	OUT_READY <= '1';

    wait until CLK'event and CLK= '1' and OUT_REQ = '0';
	OUT_READY <= '0';

	end process;

end ALGORITHM;