33_simu.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Author    : yzf
-- Created On: Thu Dec 21 09:46:16 1995
-- Testbench for comp.comp

architecture BENCH of test_comp is 
	component comp
	    PORT(
		A: IN SHORT;
		B: IN SHORT;
		IN_READY: IN BIT;
		OUT_REQ: IN BIT;
		CLK: IN BIT;
		OUT_READY: OUT BIT;
		GT: OUT BIT;
		LT: OUT BIT;
		EQ: OUT BIT
	    );
	end component;

	signal A:SHORT;
	signal B:SHORT;
	signal IN_READY:BIT;
	signal OUT_REQ:BIT;
	signal CLK:BIT;
	signal OUT_READY:BIT;
	signal GT:BIT;
	signal LT:BIT;
	signal EQ:BIT;

for all: comp use entity work.comp;
begin
	comp_I1: comp 
	    port map (
		A => A,
		B => B,
		IN_READY => IN_READY,
		OUT_REQ => OUT_REQ,
		CLK => CLK,
		OUT_READY => OUT_READY,
		GT => GT,
		LT => LT,
		EQ => EQ
	    );

	comp_driver: process
	begin
	   wait until  CLK = '1';
	   IN_READY <= '0';
	   A <= 25;
	   B <= 23; 
	   OUT_REQ <= '0';

	   wait until  CLK = '1';
	   IN_READY <= '1';

	   wait until  CLK = '1';
	   OUT_REQ <= '1';

	   wait until CLK'event and CLK = '1' and OUT_READY =  '1';
	   OUT_REQ <= '0';

	   wait until  CLK = '1';
	   IN_READY <= '0';
	   A <= 35;
	   B <= 48; 
	   OUT_REQ <= '0';

	   wait until  CLK = '1';
	   IN_READY <= '1';

	   wait until  CLK = '1';
	   OUT_REQ <= '1';

	   wait until CLK'event and CLK = '1' and OUT_READY =  '1';
	   OUT_REQ <= '0';

	   wait until  CLK = '1';
	   IN_READY <= '0';
	   A <= 58;
	   B <= 58; 
	   OUT_REQ <= '0';

	   wait until  CLK = '1';
	   IN_READY <= '1';

	   wait until  CLK = '1';
	   OUT_REQ <= '1';

	   wait until CLK'event and CLK = '1' and OUT_READY =  '1';
	   OUT_REQ <= '0';

	   assert false
	   report "---End of Simulation---"
	   severity error;

	end process;
	   CLK <= not CLK after 50 ns;
end BENCH;