18_tech_lib.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

----------------------------------------------------
-- The vhdl description for Xilinx Library (4000)
-- 
-- Category: Self-Defined Types and Functions
--
-- Yan.Zongfu
-- 1995.10.18
----------------------------------------------------

---------------------------------------------------
-- Subypes: 
--		Self-Defined Types	
---------------------------------------------------

package	types is
    subtype nat16 is integer range 0 to 65535;
    subtype nat8  is integer range 0 to 255;
    subtype nat4  is integer range 0 to 15;
    function bit_to_int(bit1: bit_vector) return integer;
    function int_to_bit(in1: integer; len:integer) return bit_vector;
end types;

---------------------------------------------------
-- Functions: 
--		Self-Defined Functions	
---------------------------------------------------
package body types is 
    function bit_to_int(bit1: bit_vector) return integer is
	ALIAS v1: BIT_VECTOR(bit1'LENGTH-1 DOWNTO 0) IS bit1;
        variable SUM: integer := 0;
        variable i: integer;
    begin
	for i in v1'length - 1 downto 0 loop
		if v1(i) = '1' then
			SUM := SUM + 2**i;
		end if;
	end loop;

	return SUM;
    end bit_to_int; 

    function int_to_bit(in1: integer; len:integer) return bit_vector is 
	variable i, in2: integer;
	variable digit1: integer:= 2**(len - 1);
	variable result: bit_vector((len-1) downto 0);
    begin
	in2 := in1;
	for i in (len - 1) downto 0 loop
		if in2 >= digit1 then
			result(i) := '1';

			in2 := in2 - digit1;
		else
			result(i) := '0';
		end if;

		digit1 := digit1 / 2;
	end loop;
	
	return result;
    end int_to_bit;
end types;

----------------------------------------------------
-- The vhdl description for Xilinx Library (4000)
-- 
-- Category: Arithmetic Functions
--
-- Yan.Zongfu
-- 1995.10.16
----------------------------------------------------

---------------------------------------------------
-- ADD1: 
--		1-Bit Full Adder with Carry-In & Carry-Out
---------------------------------------------------
use work.types.all;
entity ADD1 is port( 
	A  : in  bit;
	B  : in  bit;
	CI : in  bit;
	CO : out bit;
	S  : out bit);
end ADD1;  

architecture FUNC of ADD1 is
	signal	X, Y: bit;
begin
	X  <= A xor B;
	Y  <= X and CI;

	S  <= X xor CI;
	CO <= Y or (A and B);
end FUNC; 

---------------------------------------------------
-- ADD2: 
--		2-Bit Full Adder with Carry-In & Carry-Out
---------------------------------------------------
use work.types.all;
entity ADD2 is port( 
	A0 : in  bit;
	A1 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	CI : in  bit;
	CO : out bit;
	S0 : out bit;
	S1 : out bit);
end ADD2;  

architecture FUNC of ADD2 is
begin
	process(A0, A1, B0, B1, CI)
		variable A, B: bit_vector(1 downto 0);
		variable S: bit_vector(2 downto 0);
		variable INT_A, INT_B, INT_S: nat4;
	begin
		-- initial
		A := A1 & A0;
		B := B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- add A + B
		INT_S := INT_A + INT_B;

		-- add CI
		if CI = '1' then 
		   INT_S := INT_S + 1;
		end if;

		-- exchange INT_S to bit_vector
		S := int_to_bit(INT_S, 3);

		-- output
		S0 <= S(0);
		S1 <= S(1);
		CO <= S(2);
	end process;
end FUNC;

---------------------------------------------------
-- ADD4: 
--		4-Bit Full Adder with Carry-In & Carry-Out
---------------------------------------------------
use work.types.all;
entity ADD4 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	CI : in  bit;
	CO : out bit;
	S0 : out bit;
	S1 : out bit;
	S2 : out bit;
	S3 : out bit);
end ADD4;  

architecture FUNC of ADD4 is
begin
	process(A0, A1, A2, A3, B0, B1, B2, B3,  CI)
		variable A, B: bit_vector(3 downto 0);
		variable S: bit_vector(4 downto 0);
		variable INT_A, INT_B, INT_S: nat8;
	begin
		-- initial
		A := A3 & A2 & A1 & A0;
		B := B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- add A + B
		INT_S := INT_A + INT_B;

		-- add CI
		if CI = '1' then 
		   INT_S := INT_S + 1;
		end if;

		-- exchange INT_S to bit_vector
		S := int_to_bit(INT_S, 5);

		-- output
		S0 <= S(0);
		S1 <= S(1);
		S2 <= S(2);
		S3 <= S(3);
		CO <= S(4);
	end process;
end FUNC;

---------------------------------------------------
-- ADD8: 
--		8-Bit Full Adder with Carry-In & Carry-Out
---------------------------------------------------
use work.types.all;
entity ADD8 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	CI : in  bit;
	CO : out bit;
	S0 : out bit;
	S1 : out bit;
	S2 : out bit;
	S3 : out bit;
	S4 : out bit;
	S5 : out bit;
	S6 : out bit;
	S7 : out bit);
end ADD8;  

architecture FUNC of ADD8 is
begin
	
	process(A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B2,B3,B4,B5,B6,B7,CI)
		variable A, B: bit_vector(7 downto 0);
		variable S: bit_vector(8 downto 0);
		variable INT_A, INT_B, INT_S: nat16;
	begin
		-- initial
		A := A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- add A + B
		INT_S := INT_A + INT_B;

		-- add CI
		if CI = '1' then 
		   INT_S := INT_S + 1;
		end if;

		-- exchange INT_S to bit_vector
		S := int_to_bit(INT_S, 9);

		-- output
		S0 <= S(0);
		S1 <= S(1);
		S2 <= S(2);
		S3 <= S(3);
		S4 <= S(4);
		S5 <= S(5);
		S6 <= S(6);
		S7 <= S(7);
		CO <= S(8);
	end process;
end FUNC;

---------------------------------------------------
-- ADD16: 
--		16-Bit Full Adder with Carry-In & Carry-Out
---------------------------------------------------
use work.types.all;
entity ADD16 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	CI : in  bit;
	CO : out bit;
	S0 : out bit;
	S1 : out bit;
	S2 : out bit;
	S3 : out bit;
	S4 : out bit;
	S5 : out bit;
	S6 : out bit;
	S7 : out bit;
	S8 : out bit;
	S9 : out bit;
	S10: out bit;
	S11: out bit;
	S12: out bit;
	S13: out bit;
	S14: out bit;
	S15: out bit);
end ADD16;  

architecture FUNC of ADD16 is
begin
	
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,
			B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,CI)
		variable A, B: bit_vector(15 downto 0);
		variable S: bit_vector(16 downto 0);
		variable INT_A, INT_B, INT_S: integer;
	begin
		-- initial
		A := A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- add A + B
		INT_S := INT_A + INT_B;

		-- add CI
		if CI = '1' then 
		   INT_S := INT_S + 1;
		end if;

		-- exchange INT_S to bit_vector
		S := int_to_bit(INT_S, 17);

		-- output
		S0 <= S(0);
		S1 <= S(1);
		S2 <= S(2);
		S3 <= S(3);
		S4 <= S(4);
		S5 <= S(5);
		S6 <= S(6);
		S7 <= S(7);
		S8 <= S(8);
		S9 <= S(9);
		S10<= S(10);
		S11<= S(11);
		S12<= S(12);
		S13<= S(13);
		S14<= S(14);
		S15<= S(15);
		CO <= S(16);
	end process;
end FUNC;

---------------------------------------------------
-- ADD32: 
--		32-Bit Full Adder with Carry-In & Carry-Out
---------------------------------------------------
use work.types.all;
entity ADD32 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	A16: in  bit;
	A17: in  bit;
	A18: in  bit;
	A19: in  bit;
	A20: in  bit;
	A21: in  bit;
	A22: in  bit;
	A23: in  bit;
	A24: in  bit;
	A25: in  bit;
	A26: in  bit;
	A27: in  bit;
	A28: in  bit;
	A29: in  bit;
	A30: in  bit;
	A31: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	B16: in  bit;
	B17: in  bit;
	B18: in  bit;
	B19: in  bit;
	B20: in  bit;
	B21: in  bit;
	B22: in  bit;
	B23: in  bit;
	B24: in  bit;
	B25: in  bit;
	B26: in  bit;
	B27: in  bit;
	B28: in  bit;
	B29: in  bit;
	B30: in  bit;
	B31: in  bit;
	CI : in  bit;
	CO : out bit;
	S0 : out bit;
	S1 : out bit;
	S2 : out bit;
	S3 : out bit;
	S4 : out bit;
	S5 : out bit;
	S6 : out bit;
	S7 : out bit;
	S8 : out bit;
	S9 : out bit;
	S10: out bit;
	S11: out bit;
	S12: out bit;
	S13: out bit;
	S14: out bit;
	S15: out bit;
	S16: out bit;
	S17: out bit;
	S18: out bit;
	S19: out bit;
	S20: out bit;
	S21: out bit;
	S22: out bit;
	S23: out bit;
	S24: out bit;
	S25: out bit;
	S26: out bit;
	S27: out bit;
	S28: out bit;
	S29: out bit;
	S30: out bit;
	S31: out bit);
end ADD32;  

architecture FUNC of ADD32 is
begin
	
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,
		    A11,A12,A13,A14,A15,A16,A17,A18,A19,A20,
	        A21,A22,A23,A24,A25,A25,A27,A28,A29,A30, A31,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,
		    B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,
	        B21,B22,B23,B24,B25,B25,B27,B28,B29,B30, B31,CI)
		variable A, B: bit_vector(31 downto 0);
		variable S: bit_vector(31 downto 0);
		variable INT_A, INT_B, INT_S: integer;
	begin
		-- initial
		A := A31 & A30 & A29 & A28 & A27 & A26 & A25 & A24 & A23 & A22 & A21 & A20 & A19 & A18 & A17 & A16 & A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B31 & B30 & B29 & B28 & B27 & B26 & B25 & B24 & B23 & B22 & B21 & B20 & B19 & B18 & B17 & B16 & B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- add A + B
		INT_S := INT_A + INT_B;

		-- add CI
		if CI = '1' then 
		   INT_S := INT_S + 1;
		end if;

		-- exchange INT_S to bit_vector
		S := int_to_bit(INT_S, 32);

		-- output
		S0 <= S(0);
		S1 <= S(1);
		S2 <= S(2);
		S3 <= S(3);
		S4 <= S(4);
		S5 <= S(5);
		S6 <= S(6);
		S7 <= S(7);
		S8 <= S(8);
		S9 <= S(9);
		S10<= S(10);
		S11<= S(11);
		S12<= S(12);
		S13<= S(13);
		S14<= S(14);
		S15<= S(15);
		S16<= S(16);
		S17<= S(17);
		S18<= S(18);
		S19<= S(19);
		S20<= S(20);
		S21<= S(21);
		S22<= S(22);
		S23<= S(23);
		S24<= S(24);
		S25<= S(25);
		S26<= S(26);
		S27<= S(27);
		S28<= S(28);
		S29<= S(29);
		S30<= S(30);
		S31<= S(31);
		CO <= '0';
	end process;
end FUNC;

---------------------------------------------------------
-- ADDSUB1: 
--		1-Bit Adder/Substractor with Carry-In & Carry-Out 
--	and Fast-Carry Logic
---------------------------------------------------------
use work.types.all;
entity ADDSUB1 is port( 
	A  : in  bit;
	B  : in  bit;
	CI : in  bit;
	ADD: in  bit;
	CO : out bit;
	S  : out bit);
end ADDSUB1;  

architecture FUNC of ADDSUB1 is
begin
	process(A, B, ADD, CI)
		variable X, Y: bit;
	begin
		if ADD = '1' then			-- Adder 
			X  := A xor B;
			Y  := X and CI;

			S  <= X xor CI;
			CO <= Y or (A and B);
		else						-- Substractor
			X  := not (A xor B);	
			Y  := X and CI;

			S  <= X xor CI;
			CO <= Y or (A and not(B));
		end if;
	end process;
end FUNC; 

--------------------------------------------------
-- ADSU8H: 
--		8-Bit Adder/Substractor with Overflow and 
--	Fast-Carry Logic
--------------------------------------------------
use work.types.all;
entity ADSU8H is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	ADD: in  bit;
	OFL: out bit;
	S0 : out bit;
	S1 : out bit;
	S2 : out bit;
	S3 : out bit;
	S4 : out bit;
	S5 : out bit;
	S6 : out bit;
	S7 : out bit);
end ADSU8H;  

architecture FUNC of ADSU8H is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7, B0,B1,B2,B3,B4,B5,B6,B7,ADD)
		variable A, B: bit_vector(7 downto 0);
		variable S: bit_vector(8 downto 0);
		variable INT_A, INT_B, INT_S: nat16;
	begin
		-- initial
		A := A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		if ADD = '1' then			-- Adder 
			-- A + B
			INT_S := INT_A + INT_B;