32_test_110b.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--Page          :299,300

--Objective     :Procedure constrsain 

--Filename      :test_110b

--Author        :Joseph Pick

entity Test_110b is
end Test_110b;

architecture Behave_1 of Test_110b is
  signal A_Sig : NATURAL := 0;
  signal B_Sig : NATURAL := 0;
  signal C_Sig : NATURAL := 0;

  procedure Concur_Proc is
	   variable Count_CP : NATURAL := 0;
  begin 
    Count_CP := Count_CP +1;
    if A_Sig = 55 then 
	  Count_CP := Count_CP + 1 ;
	  wait until B_Sig =65;
	  C_Sig <= 75 after 10 ns;
    end if ;
    Count_CP :=Count_CP + 1;
  end Concur_Proc;

begin

  Gen_Signals:
  process
	variable Count_GS : Natural := 0 ;
  begin 
	wait for 10 ns;
	Count_GS := Count_GS + 1;
	A_Sig <= 55;
	wait for 10 ns;
	Count_GS := Count_GS + 1;
	B_Sig <=65;
	wait on C_Sig;
	Count_GS := C_Sig;
  end process Gen_Signals;

  Concur_Proc;

end Behave_1;