17_test_bench.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Author    : yzf
-- Created On: Mon Nov  6 09:54:13 1995
-- Testbench for parity.parity

--library	STD;
--library	WORK;
--library	parity;
--use	STD.STANDARD.ALL;
--use	PARITY.TYPES.ALL;
--use	WORK.ALL;

use work.types.all;

entity test_parity is

end test_parity;


architecture BENCH of test_parity is 
	component parity
	    PORT(
		IN0: IN BIT;
		IN1: IN BIT;
		IN2: IN BIT;
		IN3: IN BIT;
		IN4: IN BIT;
		IN5: IN BIT;
		IN6: IN BIT;
		IN7: IN BIT;
		EVEN_IN: IN BIT;
		ODD_IN: IN BIT;
		IN_READY: IN BIT;
		OUT_REQ: IN BIT;
		CLK: IN BIT;
		OUT_READY: OUT BIT;
		ODD_OUT: OUT BIT;
		EVEN_OUT: OUT BIT
	    );
	end component;

	signal IN0:BIT;
	signal IN1:BIT;
	signal IN2:BIT;
	signal IN3:BIT;
	signal IN4:BIT;
	signal IN5:BIT;
	signal IN6:BIT;
	signal IN7:BIT;
	signal EVEN_IN:BIT;
	signal ODD_IN:BIT;
	signal IN_READY:BIT;
	signal OUT_REQ:BIT;
	signal CLK:BIT;
	signal OUT_READY:BIT;
	signal ODD_OUT:BIT;
	signal EVEN_OUT:BIT;

for all:parity use entity work.parity;
begin
	parity_I1: parity 
	    port map (
		IN0 => IN0,
		IN1 => IN1,
		IN2 => IN2,
		IN3 => IN3,
		IN4 => IN4,
		IN5 => IN5,
		IN6 => IN6,
		IN7 => IN7,
		EVEN_IN => EVEN_IN,
		ODD_IN => ODD_IN,
		IN_READY => IN_READY,
		OUT_REQ => OUT_REQ,
		CLK => CLK,
		OUT_READY => OUT_READY,
		ODD_OUT => ODD_OUT,
		EVEN_OUT => EVEN_OUT
	    );

	parity_driver: process
	begin
	   wait until  clk = '1';
	   in_ready<='0';
	   in7 <= '1';
	   in6 <= '1';
	   in5 <= '0';
	   in4 <= '1';
	   in3 <= '0';
	   in2 <= '1';
	   in1 <= '1';
	   in0 <= '0';
	   odd_in <= '0';
	   even_in <= '1';

	   out_req <='0';
	   wait until clk = '1';
	   in_ready <= '1';
	   wait until clk = '1';
	   out_req <= '1';
	   wait until clk = '1';
	   in_ready <='0';
	   wait until clk'event and clk = '1' and out_ready='1';
       out_req <= '0';
	   wait for 150ns;

	   assert false
	   report "---End of Simulation---"
	   severity error;
	end process;
	clk <= not clk after 50 ns;
end BENCH;