74_tb_alarm_clock.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

entity tb_alarm_clock is
end tb_alarm_clock;

architecture test of tb_alarm_clock is
   component alarm_clock
      port(keypad      :in std_logic_vector(9 downto 0);
           key_down    :in std_logic;
           alarm_button:in std_logic;
           time_button :in std_logic;
           clk         :in std_logic;
           reset       :in std_logic;
           display     :out t_display;
           sound_alarm :out std_logic);
   end component;


   signal keypad      : std_logic_vector(9 downto 0):="0000000001";
   signal key_down    : std_logic:='0';
   signal alarm_button: std_logic:='0';
   signal time_button : std_logic:= '0';
   signal clk         : std_logic := '0';
   signal reset       : std_logic := '0';
   signal display     : t_display;
   signal sound_alarm : std_logic;

   for all: alarm_clock use entity work.alarm_clock(rtl);
begin
   u1: alarm_clock
    port map(
            keypad,
            key_down,
            alarm_button,
            time_button,
            clk,
            reset,
            display,
            sound_alarm
            );
    
   stim: process 
      procedure input_number(p_number : t_short) is
      begin
         keypad  <= keynumber(p_number);
         wait for 10  ms;
         key_down <= '1';
         wait for 400 ms;
         key_down <= '0';
      end procedure;
   begin
      ------------------- initialize ----------------
      keypad       <= keynumber(0);
      key_down     <= '0';
      alarm_button <= '0';
      time_button  <= '0';
      --
      reset <= '1';
      wait for 10 ms;
      reset <= '0';
      wait for 10 ms;
      ---------------- set ALARM : 12:34 ------------
      input_number(1);
      input_number(2);
      input_number(3);
      input_number(4);
      wait for 1 sec;
      alarm_button <= '1';
      wait for 500 ms;
      alarm_button <= '0';
      wait for 500 ms;
      ---------------- set NEWTIME : 12:32 ------------
      input_number(1);
      input_number(2);
      input_number(3);
      input_number(2);
      wait for 1 sec;
      time_button <= '1';
      wait for 500 ms;
      time_button <= '0';
      wait for 4 min;  
      -- check when at 12:34  if sound_alarm = '1';
      -- check display increase
      
      ---------------- show ALARM time -------------
      alarm_button <= '1';
      wait for 500 ms;
      alarm_button <= '0';
      wait for 8 min;  -- check if back to display time


      -------------- end of simulation ------------
      assert false report "End of simulation!"
      severity error;
   end process; -- stim

   clk <= not clk after 5 ms;

end test;