74_alarm_clock.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

entity alarm_clock is
   port(keypad      :in  std_logic_vector(9 downto 0);
		key_down    :in  std_logic;
        alarm_button:in  std_logic;
        time_button :in  std_logic;
        clk         :in  std_logic;
        reset       :in  std_logic;
        display     :out t_display;
        sound_alarm :out std_logic);
end alarm_clock;

architecture rtl of alarm_clock is
   component decoder
   port(keypad:in std_logic_vector(9 downto 0);
        value :out t_digital);
   end component;
   
   component key_buffer
   port(key     :in  t_digital ;
        clk     :in  std_logic;
        reset   :in  std_logic;
        new_time:out t_clock_time);
   end component;
   
   component alarm_counter
   port(new_current_time:in  t_clock_time;
        load_new_c      :in  std_logic;
        clk             :in  std_logic;
        reset           :in  std_logic;
        current_time    :out t_clock_time);
   end component;
   
   component alarm_reg
   port(new_alarm_time:in  t_clock_time;
        load_new_a    :in  std_logic;
        clk           :in  std_logic;
        reset         :in  std_logic;
        alarm_time    :out t_clock_time);
   end component;
   
   component alarm_controller
   port(key           :in  std_logic;
        alarm_button  :in  std_logic;
        time_button   :in  std_logic;
        clk           :in  std_logic;
        reset         :in  std_logic;
        load_new_a    :out std_logic;
        load_new_c    :out std_logic;
        show_new_time :out std_logic;
        show_a        :out std_logic);
   end component;
   
   component display_driver
   port(alarm_time    :in  t_clock_time;
        current_time  :in  t_clock_time;
        new_time      :in  t_clock_time;
        show_new_time :in  std_logic;
        show_a        :in  std_logic;
        sound_alarm   :out std_logic;
        display       :out t_display);
   end component;

   component fq_divider
   port(clk_in   :in  std_logic;
        reset    :in  std_logic;
        clk_out  :out std_logic
        );
   end component;
        
   signal inner_key     : t_digital;
   signal inner_time    : t_clock_time;
   signal inner_time_c  : t_clock_time;
   signal inner_time_a  : t_clock_time;
   signal inner_l_c     : std_logic;
   signal inner_l_a     : std_logic;
   signal inner_s_a     : std_logic;
   signal inner_s_n     : std_logic;
   signal inner_sec_clk : std_logic;

   for all: decoder use entity work.decoder(rtl);
   for all: key_buffer use entity work.key_buffer(rtl);
   for all: alarm_counter use entity work.alarm_counter(rtl);
   for all: alarm_reg use entity work.alarm_reg(rtl);
   for all: alarm_controller use entity work.alarm_controller(rtl);
   for all: display_driver use entity work.display_driver(rtl);
   for all: fq_divider use entity work.fq_divider(rtl);

begin
   ----------------  decoder --------------
   u1: decoder port map(keypad,inner_key);
   ----------------------------------------
   

   --------------  keypad buffer -----------
   u2: key_buffer port map(inner_key, key_down, reset, inner_time);
   -----------------------------------------


   -----------  alarm controller ------------
   u3: alarm_controller port map(key_down,
   							  alarm_button,
   							  time_button,
   							  clk,
   							  reset,
   							  inner_l_a,
   							  inner_l_c,
   							  inner_s_n,
   							  inner_s_a
   							  );
   -------------------------------------------


   ----------------  counter  -----------------
   u4: alarm_counter port map(
							 inner_time,
							 inner_l_c,
							 inner_sec_clk,
							 reset,
							 inner_time_c
							 );
   --------------------------------------------


   -------------  alarm register ---------------- 
   u5: alarm_reg port map(inner_time,inner_l_a,clk,reset,inner_time_a);
   -----------------------------------------------
     
   
   -------------  display divider ---------------
   u6: display_driver port map(
   						   inner_time_a,
   						   inner_time_c,
   						   inner_time,
   						   inner_s_n,
   						   inner_s_a,
   						   sound_alarm,
   						   display
   						   );
   ----------------------------------------------


   -------------- frequency divider -------------
   u7: fq_divider port map(clk,reset,inner_sec_clk);
   ----------------------------------------------


end rtl;