47_const_test.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_CONST1 is 
-----------------------------------------------------------
	generic
		(
		NUM     : std_logic
		);
	port(
		POUT: out std_logic
		);
end B_CONST1;

architecture FUNC of B_CONST1 is
begin
		POUT <=  NUM;
end FUNC;

library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_AND2 is 
-----------------------------------------------------------
port(
         I0  : in std_logic;
         I1  : in std_logic;
	        FOUT: out std_logic
	         );
end B_AND2;

architecture FUNC of B_AND2 is
begin
		FOUT <=  I0 and I1;

end FUNC;


library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_TEST is 
-----------------------------------------------------------
	port(
		D1 	: in  std_logic;
		TOUT: out std_logic
		);
end B_TEST;

architecture FUNC of B_TEST is
	component B_CONST1
	  generic
          (
		   NUM     : std_logic
		  );
	  port(
		   POUT: out std_logic 
		   );
     end component;
    component B_AND2
		port(
  	I0  : in std_logic;
            I1  : in std_logic;
	        FOUT: out std_logic
	         );
    end component;
    for U1: B_CONST1 use entity work.B_CONST1(FUNC);
	   for U2: B_AND2 use entity work.B_AND2(FUNC);
	
    signal temp1: std_logic;
begin
    U1: B_CONST1
	 generic map('1')
	     port map(
		  POUT => temp1);
    U2: B_AND2
	 port map(
		I0 => temp1,I1 => D1,FOUT => TOUT);

end FUNC;

library IEEE;
use IEEE.std_logic_1164.all;
entity test_const is 
end test_const;

architecture bench of test_const is
	component B_TEST
	port(
		D1 	: in  std_logic;
		TOUT: out std_logic
		);
end component;
	for U:B_TEST use entity work.B_TEST(FUNC);
	signal t_d1: std_logic;
	signal t_tout: std_logic;
begin
 U: B_TEST
     port map(t_d1,t_tout);
 driver:process
     begin
        t_d1 <= '0',
                     '1' after 100 ns,
                     '0' after 200 ns,
                     '1' after 300 ns;
     wait for 500 ns;
     assert false
        report "-----end of simulation---------"
        severity error;
 end process;
end bench;