70_buffer.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

---------------------
entity key_buffer is
---------------------
port(key     :in  t_digital;
     clk     :in  std_logic;
     reset   :in  std_logic;
     new_time:out t_clock_time
	 );
end key_buffer;

architecture rtl of key_buffer is
signal n_t:t_clock_time;
begin
   shift:process(reset,clk)     
   begin
      if (reset = '1') then
         n_t <= (0,0,0,0);
      elsif (clk'event and clk = '1' )then 
         for i in 3 downto 1 loop
            n_t(i) <= n_t(i-1);
         end loop;
         n_t(0) <= key;
         
      end if;
   end process;
   new_time <= n_t;
end rtl;