types.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

	function "nor" (L, R: MVL7) return MVL7;

	function "xor" (L, R: MVL7) return MVL7;

	function nxor (L, R: MVL7) return MVL7;

	function "not" (R: MVL7) return MVL7;

	function buf (R: MVL7) return MVL7;



	-----------------------------------------------------------------------
	--
	-- logical functions for composite type of MVL7_VECTOR
	--
	-----------------------------------------------------------------------

	function "and" (L, R: MVL7_VECTOR) return MVL7_VECTOR;

	function "nand" (L, R: MVL7_VECTOR) return MVL7_VECTOR;

	function "or" (L, R: MVL7_VECTOR) return MVL7_VECTOR;

	function "nor" (L, R: MVL7_VECTOR) return MVL7_VECTOR;

	function "xor" (L, R: MVL7_VECTOR) return MVL7_VECTOR;

	function nxor (L, R: MVL7_VECTOR) return MVL7_VECTOR;

	function "not" (R: MVL7_VECTOR) return MVL7_VECTOR;

	function buf (R: MVL7_VECTOR) return MVL7_VECTOR;



	-----------------------------------------------------------------------
	--
	-- resolution functions for wired signals and its attributes
	--
	-----------------------------------------------------------------------

	function WiredX (V: MVL7_VECTOR) return MVL7;

	function WiredOr (V: MVL7_VECTOR) return MVL7;

--synopsys translate_off
--	attribute REFLEXIVE of WiredX: function is TRUE;
--	attribute RESULT_INITIAL_VALUE of WiredX: function is MVL7'POS('Z');
--	attribute TABLE_NAME of WiredX: function is "TYPES.tbl_WIREDX";
--synopsys translate_on




	-----------------------------------------------------------------------
	--
	-- Definitions for wired signals (scalars and vectors)
	--
	-----------------------------------------------------------------------

	subtype DotX is WiredX MVL7;


	type BusX is array (Natural range <>) of DotX;



--synopsys synthesis_off
	-----------------------------------------------------------------------
	--
	-- conversion functions for driving various types
	--
	-----------------------------------------------------------------------

	function Drive (V: MVL7_VECTOR) return BusX;
	function Drive (V: BusX) return MVL7_VECTOR;
--synopsys synthesis_on

--synopsys translate_off
--	attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
--synopsys translate_on



--synopsys synthesis_off
	-----------------------------------------------------------------------
	--
	-- conversion functions for sensing various types
	-- (the second argument allows the user to specify the value to
	--  be returned when the network is undriven)
	--
	-----------------------------------------------------------------------

	function Sense (V: MVL7; vZ: MVL7) return MVL7;
	function Sense (V: MVL7_VECTOR; vZ: MVL7) return MVL7_VECTOR;
	function Sense (V: BusX; vZ: MVL7) return MVL7_VECTOR;
--synopsys synthesis_on


	-----------------------------------------------------------------------
	--
	--	Function: BVtoMVL7V
	--
	--	Purpose: Conversion function from BIT_VECTOR to MVL7_VECTOR
	--
	--	Mapping:	0 --> 0
	--			1 --> 1
	--
	-----------------------------------------------------------------------

	function BVtoMVL7V (V: BIT_VECTOR) return MVL7_VECTOR;


	-----------------------------------------------------------------------
	--
	--	Function: MVL7VtoBV
	--
	--	Purpose: Conversion function from MVL7_VECTOR to BIT_VECTOR
	--
	--	Mapping:	0, L --> 0
	--			1, H --> 1
	--			X --> vX if Xflag is TRUE
	--			X --> 0  if Xflag is FALSE
	--			Z --> vZ if Zflag is TRUE
	--			Z --> 0  if Zflag is FALSE
	--
	-----------------------------------------------------------------------

	function MVL7VtoBV (V: MVL7_VECTOR
--synopsys synthesis_off
		; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE
--synopsys synthesis_on
		) return BIT_VECTOR;
	

	-----------------------------------------------------------------------
	--
	--	Function: BITtoMVL7
	--
	--	Purpose: Conversion function from BIT to MVL7
	--
	--	Mapping:	0 --> 0
	--			1 --> 1
	--
	-----------------------------------------------------------------------

	function BITtoMVL7 (V: BIT) return MVL7;


	-----------------------------------------------------------------------
	--
	--	Function: MVL7toBIT
	--
	--	Purpose: Conversion function from MVL7 to BIT
	--
	--	Mapping:	0, L --> 0
	--			1, H --> 1
	--			X --> vX if Xflag is TRUE
	--			X --> 0  if Xflag is FALSE
	--			Z --> vZ if Zflag is TRUE
	--			Z --> 0  if Zflag is FALSE
	--
	-----------------------------------------------------------------------

	function MVL7toBIT (V: MVL7
--synopsys synthesis_off
		; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE
--synopsys synthesis_on
		) return BIT;



--synopsys synthesis_off
	-----------------------------------------------------------------------
	--
	--	Truth tables for unidirectional transistors
	--
	-----------------------------------------------------------------------


        -- truth table for reduce function
        constant tbl_REDUCE: MVL7_TAB1D :=
        -- ------------------------------------
        -- | X    0    1    Z    W    L    H  |
        -- ------------------------------------
           ('W', 'L', 'H', 'Z', 'W', 'L', 'H');

        constant tbl_NXFER: MVL7_TABLE :=
        ----------------------------------------------------------
        -- | Input  'X'  '0'  '1'  'Z'  'W'  'L'  'H'   |   Enable
        ----------------------------------------------------------
	          (('X', 'X', 'X', 'X', 'X', 'X', 'X'),   -- 'X'
	           ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'),   -- '0'
	           ('X', '0', '1', 'Z', 'W', 'L', 'H'),   -- '1'
	           ('X', 'X', 'X', 'X', 'X', 'X', 'X'),   -- 'Z'
	           ('X', 'X', 'X', 'X', 'X', 'X', 'X'),   -- 'W'
	           ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'),   -- 'L'
	           ('X', '0', '1', 'Z', 'W', 'L', 'H'));  -- 'H'
    
        constant tbl_PXFER: MVL7_TABLE :=
        ----------------------------------------------------------
        -- | Input  'X'  '0'  '1'  'Z'  'W'  'L'  'H'   |   Enable
        ----------------------------------------------------------
	          (('X', 'X', 'X', 'X', 'X', 'X', 'X'),   -- 'X'
	           ('X', '0', '1', 'Z', 'W', 'L', 'H'),   -- '0'
	           ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'),   -- '1'
	           ('X', 'X', 'X', 'X', 'X', 'X', 'X'),   -- 'Z'
	           ('X', 'X', 'X', 'X', 'X', 'X', 'X'),   -- 'W'
	           ('X', '0', '1', 'Z', 'W', 'L', 'H'),   -- 'L'
	           ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'));  -- 'H'
--synopsys synthesis_on
    
end TYPES;




package body TYPES is


	-----------------------------------------------------------------------
	--
	-- logical functions for scalar type of MVL7
	--
	-----------------------------------------------------------------------

	function "and" (L, R: MVL7) return MVL7 is
	  -- pragma built_in SYN_AND
	begin
--synopsys synthesis_off
		return tbl_AND(L, R);
--synopsys synthesis_on
	end "and";



	function "nand" (L, R: MVL7) return MVL7 is
	  -- pragma built_in SYN_NAND
	begin
--synopsys synthesis_off
		return tbl_NOT(tbl_AND(L, R));
--synopsys synthesis_on
	end "nand";



	function "or" (L, R: MVL7) return MVL7 is
	  -- pragma built_in SYN_OR
	begin
--synopsys synthesis_off
		return tbl_OR(L, R);
--synopsys synthesis_on
	end "or";



	function "nor" (L, R: MVL7) return MVL7 is
	  -- pragma built_in SYN_NOR
	begin
--synopsys synthesis_off
		return tbl_NOT(tbl_OR(L, R));
--synopsys synthesis_on
	end "nor";



	function "xor" (L, R: MVL7) return MVL7 is
	  -- pragma built_in SYN_XOR
	begin
--synopsys synthesis_off
		return tbl_XOR(L, R);
--synopsys synthesis_on
	end "xor";


	function nxor (L, R: MVL7) return MVL7 is
	  -- pragma built_in SYN_XNOR
	begin
--synopsys synthesis_off
		return tbl_NOT(tbl_XOR(L, R));
--synopsys synthesis_on
	end nxor;


	function "not" (R: MVL7) return MVL7 is
	  -- pragma built_in SYN_NOT
	begin
--synopsys synthesis_off
		return tbl_NOT(R);
--synopsys synthesis_on
	end "not";


	function buf (R: MVL7) return MVL7 is
	  -- pragma built_in SYN_BUF
	begin
--synopsys synthesis_off
		return tbl_BUF(R);
--synopsys synthesis_on
	end buf;



	-----------------------------------------------------------------------
	--
	-- logical functions for composite type of MVL7_VECTOR
	--
	-----------------------------------------------------------------------

	function "and" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
	  -- pragma built_in SYN_AND
--synopsys synthesis_off
		alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
		alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
		variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
	begin
--synopsys synthesis_off
		assert L'length = R'length;
		for i in result'range loop
			result (i) := tbl_AND(LV (i), RV (i));
		end loop;
		return result;
--synopsys synthesis_on
	end "and";


	function "nand" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
	  -- pragma built_in SYN_NAND
--synopsys synthesis_off
		alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
		alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
		variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
	begin
--synopsys synthesis_off
		assert L'length = R'length;
		for i in result'range loop
			result (i) := tbl_NOT(tbl_AND(LV (i), RV (i)));
		end loop;
		return result;
--synopsys synthesis_on
	end "nand";


	function "or" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
	  -- pragma built_in SYN_OR
--synopsys synthesis_off
		alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
		alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
		variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
	begin
--synopsys synthesis_off
		assert L'length = R'length;
		for i in result'range loop
			result (i) := tbl_OR(LV (i), RV (i));
		end loop;
		return result;
--synopsys synthesis_on
	end "or";


	function "nor" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
	  -- pragma built_in SYN_NOR
--synopsys synthesis_off
		alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;