27_test_16.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Page        :  285,286

--Objective    :  Blocks and 'EVENT vs.'STABLE

--Filename     :  test_16

--Author       :  Joseph Pick 

entity Test_16 is
end Test_16;

architecture Behave_1 of Test_16 is
  signal Source : NATURAL := 0;
  signal Destination_1 : NATURAL := 0;
  signal Destination_2 : NATURAL := 0;
  signal Destination_3 : NATURAL := 0;
  signal Destination_4 : NATURAL := 0;
  signal Clock : BIT := '0';
begin 

  Blck_Test_1:
  block (clock = '1' and Clock'EVENT)
  begin 
	Destination_1 <= guarded Source;
	Destination_2 <= Source;
  end block Blck_Test_1;

  Blck_Test_2:
  block (Clock = '1' and not(Clock'STABLE))
  begin 
	Destination_3 <=guarded Source;
	Destination_4 <=Source;
  end block Blck_Test_2;

  Monitor:
  process
	variable Source_Var : NATURAL;
	variable Dest_1_Var: NATURAL;
	variable Dest_2_Var: NATURAL;
	variable Dest_3_Var: NATURAL;
	variable Dest_4_VAr: NATURAL;
  begin 
	Source_Var := Source;
	Dest_1_Var := Destination_1;
	Dest_2_Var := Destination_2;
	Dest_3_Var := Destination_3;
	Dest_4_Var := Destination_4;
	wait on Destination_1,Destination_2,
			Destination_3,Destination_4;
  end process Monitor;

  Tick_Tock:
  process
  begin
	wait for 10 ns;
	Clock <=not clock;
  end process Tick_Tock;

  Source_Wave: Source <=1 after 8 ns, 2 after 15 ns,
						3 after 16 ns,4 after 17 ns,
						5 after 18 ns,6 after 19 ns;
 end Behave_1;