52_divider.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- (C) Copyright 1996 Doulos  All Rights Reserved
--  Solution for Counter

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_arith.all;

entity DIVIDER is
  port (CLK_IN  : in Std_logic;
        RESET   : in Std_logic;
        SPD     :in Integer;
        CLK_OUT :out Std_logic);
end;

architecture RTL of DIVIDER is
  signal Cnt: Std_ULogic_Vector (7 downto 0);
begin
  DIVIDE: process (CLK_IN, RESET)
  begin
    if RESET = '1' then
      Cnt <= "00000000";
    elsif CLK_IN'event and CLK_IN = '1' then
      Cnt <= Cnt + "1";
    end if;
end process;

SELECT_SPEED: process (Cnt, SPD)
  begin
     CASE SPD IS
          WHEN 0 =>CLK_OUT<=Cnt(0);
          WHEN 1 =>CLK_OUT<=Cnt(1);
          WHEN 2 =>CLK_OUT<=Cnt(2);
          WHEN 3 =>CLK_OUT<=Cnt(3);
          WHEN 4 =>CLK_OUT<=Cnt(4);
          WHEN 5 =>CLK_OUT<=Cnt(5);
          WHEN 6 =>CLK_OUT<=Cnt(6);
          WHEN 7 =>CLK_OUT<=Cnt(7);
          WHEN OTHERS=>CLK_OUT<=Cnt(7);
    END CASE;
end process;
end;