31_test_35b.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

-- Page		 	: 353 - 354 
--
-- Objective 	: array signal multiplexing : error 
--
-- File Name 	: test_35b.vhd
--
-- Author    	: Joseph Pick
--


entity Test_35b is
end Test_35b;

architecture Behave_1 of Test_35b is

	type LX01 is ('X','0','1');
	type LX01_Vector is array (NATURAL range <>) of LX01;
	signal X		: LX01_Vector(3 downto 0) :=
								 (others => 'X');
	signal X_Proc_1	: LX01_Vector(3 downto 0) :=
						 (others => '0');
	signal X_Proc_2	: LX01_Vector(3 downto 0) :=
						 (others => '0');
	signal Set_X_Proc_1_2 : BOOLEAN := FALSE;
	signal Set_X_Proc_2_3 : BOOLEAN := FALSE;
	signal Count_1		  : NATURAL := 0;
	signal Count_2		  : NATURAL := 0;

begin

	Proc_1:
	process
	begin
		wait until Set_X_Proc_1_2 = TRUE;
		X_Proc_1(2) <= '1';
		wait for 200 ns;
		Count_1 <= Count_1 + 1;
	end process Proc_1;

	Proc_2:
	process
	begin
		wait until Set_X_Proc_2_3 = TRUE;
		X_Proc_2(3) <= '1';
		wait for 45 ns;
		Count_2 <= Count_2 +1;
	end process Proc_2;

	X <= X_Proc_1 when not X_Proc_1'QUIET else
		 X_Proc_2 when not X_Proc_2'QUIET else
		 X;
	Set_X_Proc_1_2 <= TRUE after 10 ns, FALSE after 400 ns;
	Set_X_Proc_2_3 <= TRUE after 50 ns, FALSE after 500 ns;

	process
	begin
		wait for 500 ns;
		assert false
		report "End of Simulation"
		severity error;
	end process;
end Behave_1;