39_wst0dp.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library IEEE;
use IEEE.std_logic_1164.all;
library dsp_lib;
use dsp_lib.delay_macro.all;
use dsp_lib.logic_pack.all;
use dsp_lib.const_pack.all;

------------------------------------------
entity wst0dp is
------------------------------------------
	port(
			b53  : in std_logic;
			b72  : in std_logic;
			i5   : in std_logic;
			i6   : in std_logic;
			m96  : in std_logic;

			k    : std_logic_vector( 8 downto 0 );
			----------------------------------------
			w44  : out std_logic;

			DRB  : std_logic_vector( 15 downto 7 ));
end wst0dp;

architecture struc of wst0dp is

	-----------------------------------
	component wst0dp01 
	-----------------------------------
		port(
				b72  :  in std_logic;
				i5   :  in std_logic;
				i6   :  in std_logic;
				m96  :  in std_logic;
				inn  :  in std_logic;

				outt :  out std_logic;
				OB   :  out std_logic
			);
	end component wst0dp01;

	-------------------------------------
	component wst0dp02
 	-------------------------------------
		port(
				b72  : in std_logic;
				i5   : in std_logic;
				i6   : in std_logic;
				inn  : in std_logic;

				outt : out std_logic;
				x    : out std_logic 
			);
	end component;

	-------------------------------------
	component wst0dp03
	------------------------------------
		port(
				b72  : in std_logic;
				i5   : in std_logic;
				i6   : in std_logic;
				m96  : in std_logic;
				inn  : in std_logic;

				outt : out std_logic;
				OB   : out std_logic;
				y4   : out std_logic 
			);
	end component;

	--signal s_b72 : std_logic;
	--signal s_i5  : std_logic;
	--signal s_i6  : std_logic;
	--signal s_m96 : std_logic;

	--signal s_b53 : std_logic;

	--signal s_k   : std_logic_vector( 8 downto 0 );

	signal s_DRB : std_logic_vector( 15 downto 11 );
	signal s_y4  : std_logic;

	begin
			
		LINE: for I in 8 downto 0 generate

			------------------------------------------------------------
			LINE9_5: if i < 9 and i > 3 generate 
				Udp02: wst0dp02
						port map( b72,i5,i6,k(I),k(I),DRB(I+7));
					s_DRB(I+7) <= DRB(I+7);
			end generate;
			------------------------------------------------------------
			LINE4  : if i = 3 generate
				Udp03: wst0dp03
						port map( b72,i5,i6,m96,k(I),k(I),y4,DRB(I+7));
					s_y4 <= y4;
			end generate;
			------------------------------------------------------------
			LINE3_0: if i <3 and i >= 0 generate
				Udp01: wst0dp01
						port map( b72,i5,i6,m96,k(I),k(I),DRB(I+7));
			end generate;
			------------------------------------------------------------

		end generate;

		process:
			wait on b53,s_DRB,s_y4;
			begin
				if b53 & s_DRB(15) & s_DRB(14) & s_DRB(13) & s_DRB(12) & s_DRB(11) & s_y4 = '1' then
					w44 <= b53;
				else w44 <= w44;
				end if;
		end process;

end struc;