3_mul.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 20 行

entity mul is
   port ( 
	  in1  : bit_vector;
	  in2  : bit_vector;
	  cntl : bit;
	  pout : out bit_vector
   );
end mul;  

architecture func of mul is
begin
   process(cntl)
   begin
	  if (cntl = '1') then
		 pout <= in1*in2;
      end if;
   end process;
end  func;