92_wss_stringreg.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--the mem_string
LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.std_logic_arith.all;
  --unsigned.ALL;
  USE work.pkg_types.ALL;
  USE work.pkg_components.ALL;

ENTITY mem_string IS
PORT ( clk        :   IN  bit1 ;
       reset      :   IN  bit1 ;
       sel_read   :   IN  bit1 ;
       s_sel      :   IN  bit1 ;
       burst      :   IN  bit2_r ;
       s_req      :   OUT  bit1 ;
       s_ack      :   IN  bit1 ;
       s_valid    :   IN  bit1 ;
       data_in    :   IN  bit8 ;
       s_ad       :   IN  bit5 ;
       s          :   out  bit8 ;
       s_done     :   out  bit1 );
END mem_string;

ARCHITECTURE behavior OF mem_string IS
SIGNAL  a1,addr       :  bit5_r;
SIGNAL  sel_write     :  bit1;
BEGIN
 PROCESS
  --地址初始化
  PROCEDURE init (burst : IN  bit2_r;SIGNAL a1 : OUT bit5_r) IS
  BEGIN 
     addr <= burst & "000";
     a1   <= burst & "000";
  END init;
  --写RAM，即更新相应地址信号
  PROCEDURE write_ram ( sel_write : IN bit1; data : IN bit8) IS
  BEGIN
     a1   <= addr;
  END write_ram;

  BEGIN
   --初始化信号值
   s_req <= '0';
   s_done <= '1';
   addr <= "00000";
   sel_write <= '0';

   --直到mem_string为工作状态且被选中，当时钟上升沿到来时，
   WAIT  UNTIL (s_sel = '1' AND rising_edge(clk) AND reset='1');
   
   --找到相应burst的开始位置，并且置mem_string为写入状态
   init(burst,addr);
   s_done <= '0';
   s_req <= '1';
   
   WAIT UNTIL ((s_ack='1' AND rising_edge(CLK)) OR reset/='1');
   --得到应答信号s_ack后，撤消s_req信号
   s_req <= '0';
   
   write_loop  : LOOP
       --等到addr有效且地址信号不为边界
       --因为一个burst设定为8个字符
       IF s_valid/='1' AND addr/=7 AND addr/=15 AND addr<23 THEN
              WAIT UNTIL ((s_valid='1' AND rising_edge(clk)) OR reset/='1');
              --复位则退出
              IF reset/='1' THEN 
                   EXIT write_loop;
              END IF;
       END IF;
       --写入8个字符，一个字符为8位
       addr <= addr +1;
       write_ram(sel_write,data_in);
       --写入完成后，写信号置位防止写入不正确的数据
       sel_write <= '1';
       --当地址达到边界或mem_string复位时退出
       IF addr=7 OR addr=15 OR addr>=23 OR reset/='1' THEN
              WAIT UNTIL rising_edge(clk);
              EXIT write_loop;
       END IF;

       WAIT UNTIL rising_edge(clk);
       sel_write <='0';
   END LOOP write_loop;
  END PROCESS;
 
  string_mem :mem_24x8
  PORT MAP (s,data_in,s_ad,a1,sel_read,sel_write,clk);

END behavior;