84_reg.vhd

来自「北京里工大学ASIC设计研究所的100个 VHDL程序设计例子」· VHDL 代码 · 共 54 行

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--
--   AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source:  AMD data book
--
--------------------------------------------------------------------------------

library l2901_lib;
use l2901_lib.types.all;
use l2901_lib.MVL7_functions.all;
use l2901_lib.synthesis_types.all;

entity reg is
port (
      RLD_BAR : in MVL7;
         load : in MVL7;
         decr : in MVL7;
          clk : in bit ;--clock;
            D : in MVL7_VECTOR(11 downto 0);
	   RE : inout MVL7_VECTOR(11 downto 0);
    Rzero_bar : out MVL7
      );
end reg;

architecture reg of reg is

begin

-------------------------------------------------------------------------------

reg_ctr : block ( (clk = '1') and (not clk'stable) )

begin

RE <= guarded D WHEN (( load = '1') or (RLD_BAR = '0')) ELSE    -- load
          RE - "000000000001" WHEN (decr = '1') and (RLD_BAR = '1') ELSE  -- decr
          RE ;   -- hold

Rzero_bar <= RE(0) or RE(1) or RE(2) or RE(4) or RE(5) or RE(6) or RE(7) or RE(8) or RE(9) or RE(10) or RE (11);

end block reg_ctr;

-------------------------------------------------------------------------------

end reg;