23_test_120.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--Page          :309,310,311,312

--Objective     :Circuit oscillation

--Filename      :test_120.vhd

--Author        :Joseph Pick

entity Nor_Gate_Bit is
  port (Ain : in BIT;Bin : in BIT; Cout : out BIT);
end Nor_Gate_Bit;

architecture Behave_1 of Nor_Gate_Bit is
 
begin 

  Gate:
  process
  begin
	Cout <= Ain nor Bin;
	wait on Ain ,Bin;
  end process Gate;
end Behave_1;

entity RS_Flip_Flop_Bit is
  port (Set : in BIT; Reset : in BIT; Q : out BIT; Q_Bar : out BIT);
end RS_Flip_Flop_Bit;

architecture Behave_1 of RS_Flip_Flop_Bit is

  component Nor_Gate_Bit
			port (Ain : in BIT; Bin : in BIT; Cout : out BIT);
  end component;

  signal Temp_Q    : BIT := '0';
  signal Temp_Q_Bar : BIT := '1';

begin 
 Out_Q     : Nor_Gate_Bit
			 port map (Ain => Reset,
					   Bin => Temp_Q_Bar,
					   Cout => Temp_Q);
 Out_Q_Bar : Nor_Gate_Bit
			 port map (Ain => Set,
					   Bin => Temp_Q,
					   Cout => Temp_Q_Bar);
 Q       <= Temp_Q;
 Q_Bar <= Temp_Q_Bar;

 Intermediate_Monitor:
 process
   variable Temp_Q_Var    : BIT := '0';
   variable Temp_Q_Bar_Var: BIT := '0';
 begin
   Temp_Q_Var := Temp_Q_Bar;
   Temp_Q_Bar_Var := Temp_Q_Bar;
   wait on Temp_Q,Temp_Q_Bar;
 end process Intermediate_Monitor;
end Behave_1;

entity Test_120 is 
end test_120;

architecture Behave_1 of Test_120 is

  component RS_Flip_Flop_Bit
	 port (Set : in BIT; Reset : in BIT;
		   Q : out BIT; Q_Bar : out BIT);
  end component;
  
  signal Set    : BIT := '0';
  signal Reset  : BIT := '0';
  signal Q      : BIT := '0';
  signal Q_Bar  : BIT := '0';

begin 
  RS_FF_1: RS_Flip_Flop_Bit
		   port map (Set => Set,Reset =>  Reset,
					 Q => Q, Q_Bar => Q_Bar);

  RS_Stimulus:
  process
	 variable  Stimulus_Count : NATURAL := 0;
  begin 
	Set <= '1' after 5 ns, '0' after 10 ns;
	Stimulus_Count := Stimulus_Count + 1;
	wait for 40 ns;
  end  process RS_Stimulus;

  RS_Monitor:
  process
	variable Q_Var      : BIT := '0';
	variable Q_Bar_Var  : BIT := '0';
  begin 
	Q_Var      := Q;
	Q_Bar_Var  := Q_Bar;
	wait on Q,Q_Bar;
  end process RS_Monitor;

end Behave_1;

configuration Config_Test_120 of Test_120 is
  for Behave_1
	 for RS_FF_1 : RS_Flip_Flop_Bit
	   use entity WORK.RS_Flip_Flop_Bit(Behave_1);
	   for Behave_1
		  for all : Nor_Gate_Bit
			  use entity WORK.Nor_Gate_Bit(Behave_1);
		  end for;
       end for;
  	 end for;
   end for;
end Config_Test_120;