71_tb_alarm_reg.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

entity tb_alarm_reg is
end tb_alarm_reg;

architecture test of tb_alarm_reg is
component alarm_reg       
       port(new_alarm_time:in t_clock_time;
            load_new_a    :in std_logic;
            clk         :in std_logic;
            reset         :in std_logic;
            alarm_time    :out t_clock_time);
end component;

signal new_alarm_time:t_clock_time;
signal load_new_a:std_logic;
signal clk:std_logic;
signal reset:std_logic;
signal alarm_time:t_clock_time;

for all:alarm_reg use entity work.alarm_reg(rtl);

begin
u1:alarm_reg
   port map(new_alarm_time,load_new_a,clk,reset,alarm_time);

stim:process
  begin
  --initialize
  reset <= '1';
  load_new_a <= '1';
  new_alarm_time <= (2,0,0,0);

  wait for 20 ns;
  --test vector1
  reset <= '0';
  load_new_a <= '0';
  new_alarm_time <= (1,3,5,4);

  wait for 100 ns;
  --test vector2
  reset <= '0';
  load_new_a <= '1';
  new_alarm_time <= (1,6,0,9);

  wait for 100 ns;
  --test vector3
  reset <= '0';
  load_new_a <= '1';
  new_alarm_time <= (0,0,0,8);

  wait for 100 ns;
  assert false report "End of simulation!"
  severity error;
  end process;

clk_gen:process
  begin
  clk <= '0';
  while true loop
      wait for 50 ns;
      clk <= not clk;
  end loop;
  end process;
end test;