71_alarm_reg.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--                             _ _
--                              L   
---------------------------OO-------OO---------------------------------
--                                                                   --
-- DESCRIPTION : training files                                      --
-- Author      : Chen DongYing & Zhang DongXiao                      --
-- AFFILIATION : ASIC Research Center of B.I.T.                      --
-- DATE        : 1999.06 14-20                                       --
-- COPYRIGHT   : (c) 1999-2001, Mentor China                         --
--                              ASIC Research Center of B.I.T.       --
--                                                                   --
-- This source file may be used and distributed without restriction  --
-- provided that this copyright statement is not removed  from  the  --
-- file and that any derivative work contains this copyright notice. --
--                                                                   --
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

-------------------
entity alarm_reg is
-------------------
   port(new_alarm_time:in  t_clock_time;
        load_new_a    :in  std_logic;
        clk           :in  std_logic;
        reset         :in  std_logic;
        alarm_time    :out t_clock_time
		);
end alarm_reg;

architecture rtl of alarm_reg is
begin
   process(clk,reset)
   begin
      if reset = '1' then
         alarm_time <= (0,0,0,0);
      else
         if rising_edge(clk) then
            if load_new_a = '1' then
               alarm_time <= new_alarm_time;
            elsif load_new_a /= '0' then
               assert false report "Uncertain load_new_alarm control!"
               severity warning;
            end if;
         end if;
      end if;
   end process;
end rtl;